| Message ID | 1489711910-17443-1-git-send-email-mdf@kernel.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
On 17.3.2017 01:51, Moritz Fischer wrote: > This adds the binding documentation for the Xilinx LogiCORE PR > Decoupler soft core. > > Signed-off-by: Moritz Fischer <mdf@kernel.org> > Cc: Michal Simek <michal.simek@xilinx.com> > Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> > Cc: linux-kernel@vger.kernel.org > Cc: devicetree@vger.kernel.org > --- > > Changes from v1: > - Added clock names & clock to example > - Merged some of the description from Michal's version > > --- > .../bindings/fpga/xilinx-pr-decoupler.txt | 32 ++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt > > diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt > new file mode 100644 > index 0000000..2080006 > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt > @@ -0,0 +1,32 @@ > +Xilinx LogiCORE Partial Reconfig Decoupler Softcore > + > +The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more > +decouplers / fpga bridges. > +The controller can decouple/disable the bridges which prevents signal > +changes from passing through the bridge. The controller can also > +couple / enable the bridges which allows traffic to pass through the > +bridge normally. > + > +The Driver supports only MMIO handling. A PR region can have multiple > +PR Decouples which can bhe handled independently or chaines via decouple/ > +decouple_status signals. > + > +Required properties: > +- compatible : Should contain "xlnx,pr-decoupler-1.00" should I would tend to do this as "xlnx,pr-decoupler-1.00" and/or "xlnx,pr_decoupler" > +- regs : base address and size for decoupler module > +- clocks : input clock to IP > +- clock-names : should contain "aclk" > + > +Optional properties: > +- bridge-enable : 0 if driver should disable bridge at startup > + 1 if driver should enable bridge at startup > + Default is to leave bridge in current state. Interesting that this is not a bool. But anyway this should be link to bridge binding because I expect this is the same for all. > + > +Example: > + fpga-bridge@100000450 { > + compatible = "xlnx,pr-decoupler-1.00"; "xlnx,pr-decoupler-1.00", "xlnx,pr_decoupler"; > + regs = <0x1000 0x10>; > + clocks = <&clkc 15>; > + clock-names = "aclk"; > + bridge-enable = <0>; > + }; > Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe linux-fpga" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file mode 100644 index 0000000..2080006 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt @@ -0,0 +1,32 @@ +Xilinx LogiCORE Partial Reconfig Decoupler Softcore + +The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more +decouplers / fpga bridges. +The controller can decouple/disable the bridges which prevents signal +changes from passing through the bridge. The controller can also +couple / enable the bridges which allows traffic to pass through the +bridge normally. + +The Driver supports only MMIO handling. A PR region can have multiple +PR Decouples which can bhe handled independently or chaines via decouple/ +decouple_status signals. + +Required properties: +- compatible : Should contain "xlnx,pr-decoupler-1.00" +- regs : base address and size for decoupler module +- clocks : input clock to IP +- clock-names : should contain "aclk" + +Optional properties: +- bridge-enable : 0 if driver should disable bridge at startup + 1 if driver should enable bridge at startup + Default is to leave bridge in current state. + +Example: + fpga-bridge@100000450 { + compatible = "xlnx,pr-decoupler-1.00"; + regs = <0x1000 0x10>; + clocks = <&clkc 15>; + clock-names = "aclk"; + bridge-enable = <0>; + };
This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core. Signed-off-by: Moritz Fischer <mdf@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org --- Changes from v1: - Added clock names & clock to example - Merged some of the description from Michal's version --- .../bindings/fpga/xilinx-pr-decoupler.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt