From patchwork Tue Mar 21 21:02:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Gerlach X-Patchwork-Id: 9637609 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 50C7060328 for ; Tue, 21 Mar 2017 21:12:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4167D25E13 for ; Tue, 21 Mar 2017 21:12:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 34B8027D8D; Tue, 21 Mar 2017 21:12:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B0AB127C14 for ; Tue, 21 Mar 2017 21:12:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934000AbdCUVMB (ORCPT ); Tue, 21 Mar 2017 17:12:01 -0400 Received: from mga14.intel.com ([192.55.52.115]:12322 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933367AbdCUVL6 (ORCPT ); Tue, 21 Mar 2017 17:11:58 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490130717; x=1521666717; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=WEGsAcKmntUjtwpMGTP4tWDISzX8cCXTq7Mz8P/Z48c=; b=atxlawp6ZkSF9ROZYYxtti0WYCthhcH2SUZMFERBEYKqrPhB3APwDAyf 8TwEfGF6+3o/YwIH9CGF92yWbuawrw==; Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Mar 2017 14:02:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,201,1486454400"; d="scan'208";a="946779359" Received: from mgerlach-mobl.amr.corp.intel.com (HELO mgerlach-VirtualBox.amr.corp.intel.com) ([10.254.181.80]) by orsmga003.jf.intel.com with ESMTP; 21 Mar 2017 14:02:44 -0700 From: matthew.gerlach@linux.intel.com To: atull@kernel.org, moritz.fischer@ettus.com, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, agust@denx.de Cc: Alan Tull Subject: [PATCH v6 1/4] fpga: add config complete timeout Date: Tue, 21 Mar 2017 14:02:36 -0700 Message-Id: <1490130159-2597-2-git-send-email-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490130159-2597-1-git-send-email-matthew.gerlach@linux.intel.com> References: <1490130159-2597-1-git-send-email-matthew.gerlach@linux.intel.com> Sender: linux-fpga-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Alan Tull Adding timeout for maximum allowed time for FPGA to go to operating mode after a FPGA region has been programmed. Signed-off-by: Alan Tull --- drivers/fpga/fpga-region.c | 3 +++ include/linux/fpga/fpga-mgr.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/fpga/fpga-region.c b/drivers/fpga/fpga-region.c index 2fe2a52..ae4c61a 100644 --- a/drivers/fpga/fpga-region.c +++ b/drivers/fpga/fpga-region.c @@ -385,6 +385,9 @@ static int fpga_region_notify_pre_apply(struct fpga_region *region, of_property_read_u32(nd->overlay, "region-freeze-timeout-us", &info->disable_timeout_us); + of_property_read_u32(nd->overlay, "config-complete-timeout-us", + &info->config_complete_timeout_us); + /* If FPGA was externally programmed, don't specify firmware */ if ((info->flags & FPGA_MGR_EXTERNAL_CONFIG) && firmware_name) { pr_err("error: specified firmware and external-fpga-config"); diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index e2ef94f..b4ac24c 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -77,11 +77,14 @@ enum fpga_mgr_states { * @flags: boolean flags as defined above * @enable_timeout_us: maximum time to enable traffic through bridge (uSec) * @disable_timeout_us: maximum time to disable traffic through bridge (uSec) + * @config_complete_timeout_us: maximum time for FPGA to switch to operating + * status in the write_complete op. */ struct fpga_image_info { u32 flags; u32 enable_timeout_us; u32 disable_timeout_us; + u32 config_complete_timeout_us; }; /**