From patchwork Fri Jun 2 10:27:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Paolo Pisati X-Patchwork-Id: 9762201 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 81E40602BF for ; Fri, 2 Jun 2017 10:27:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7CFE228517 for ; Fri, 2 Jun 2017 10:27:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 714332853B; Fri, 2 Jun 2017 10:27:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C9A2B28517 for ; Fri, 2 Jun 2017 10:27:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751160AbdFBK1c (ORCPT ); Fri, 2 Jun 2017 06:27:32 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:35400 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751173AbdFBK1T (ORCPT ); Fri, 2 Jun 2017 06:27:19 -0400 Received: by mail-wm0-f67.google.com with SMTP id g15so17900451wmc.2; Fri, 02 Jun 2017 03:27:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fj/6EBVSCvehtp9j5xUtan9qAxzQv3o3owN8Dcdk6e8=; b=C7Sli3WlHee03ci0JNF9fKJIeQqFvBPIn12lJ5fQrYPPTI3PN26EFz5xLIlIYDack7 tddUg2rf6itXkt+LmexMc34H7A8dyOoBJfWNcDJWWZCq2dlfcenprVrNpJAHFCetc0rH d3/I51oQ/wkI4eIlylHCG/owqpHNHPp1gzLcdTytZo+Q8m/IHcxOZUpYx2lcF18819og Zv9DwggBPbRwtHSjDrIMDvVXoDIbEvBKU4a3PJiAPPOyEV5N8FJCOrIf4o961LYWwz6f sddRFQ1oUUG0/pLnZhIoKGO0DxYCPIosc98APkUUBTzViJ31A/53+IF+e/IfBPO1sWlV sYGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fj/6EBVSCvehtp9j5xUtan9qAxzQv3o3owN8Dcdk6e8=; b=Rmy8FHLm5IGDNHkt9i10LJZiRkWXT+TJqHkMT1iO8zqRJt2TGpstVEVlB1XoN10JaS zZVmp2JibmK6Yd/MWpv4qpsufAGGVMQlWtoj14+0mxUCX3uJxFqsyYCJ2RNZu9DQGx/a BH3z8lYbM+5+1fbnJpjusFto8uh9tPTtq+T/G2jwb34rL5VcbsusyTcmg5DtdFJQeVoc 4GIEdcEgf93JpbYYjBCsnxeqA2Rcvu0ttc8bNdL9rFzEnP/CgjvOD/vAtTwMWlsUunjb PS+8Q9uYYxf6DoeLkuxL/rrNC3h1JVyBx5d7NHcHUAyom5BvaS0UP2i+1Qb15QJRx7nr 0eyQ== X-Gm-Message-State: AODbwcACUjBTN/J4Ibq0jNvaecTAvYL2LBHSQKuejXKX6oY9FuXFhl8+ QoZJKDXb7x4tgA== X-Received: by 10.223.134.22 with SMTP id 22mr4228376wrv.182.1496399237211; Fri, 02 Jun 2017 03:27:17 -0700 (PDT) Received: from gmail.com (net-93-146-98-251.cust.vodafonedsl.it. [93.146.98.251]) by smtp.gmail.com with ESMTPSA id i3sm2086158wmb.13.2017.06.02.03.27.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 Jun 2017 03:27:16 -0700 (PDT) From: Paolo Pisati To: Alan Tull , Moritz Fischer , Mark Rutland , Rob Herring Cc: linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/2] fpga: lattice machxo2: Add Lattice MachXO2 support Date: Fri, 2 Jun 2017 12:27:13 +0200 Message-Id: <1496399233-21451-3-git-send-email-p.pisati@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1496399233-21451-1-git-send-email-p.pisati@gmail.com> References: <1496399233-21451-1-git-send-email-p.pisati@gmail.com> MIME-Version: 1.0 Sender: linux-fpga-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support to the FPGA manager for programming MachXO2 device’s internal flash memory, via slave SPI. Signed-off-by: Paolo Pisati --- drivers/fpga/Kconfig | 7 ++ drivers/fpga/Makefile | 1 + drivers/fpga/machxo2-spi.c | 277 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 285 insertions(+) create mode 100644 drivers/fpga/machxo2-spi.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index c81cb7d..cce135b 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -26,6 +26,13 @@ config FPGA_MGR_ICE40_SPI help FPGA manager driver support for Lattice iCE40 FPGAs over SPI. +config FPGA_MGR_MACHXO2_SPI + tristate "Lattice MachXO2 SPI" + depends on SPI + help + FPGA manager driver support for Lattice MachXO2 configuration + over slave SPI interface. + config FPGA_MGR_SOCFPGA tristate "Altera SOCFPGA FPGA Manager" depends on ARCH_SOCFPGA || COMPILE_TEST diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index c6f5d74..cdab1fe 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_FPGA) += fpga-mgr.o # FPGA Manager Drivers obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o +obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/machxo2-spi.c new file mode 100644 index 0000000..ea8793c --- /dev/null +++ b/drivers/fpga/machxo2-spi.c @@ -0,0 +1,277 @@ +/** + * Lattice MachXO2 Slave SPI Driver + * + * Copyright (C) 2017 Paolo Pisati + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * Manage Lattice FPGA firmware that is loaded over SPI using + * the slave serial configuration interface. + */ + +#include +#include +#include +#include +#include +#include + +/* MachXO2 Programming Guide - sysCONFIG Programming Commands */ + +#define ISC_DISABLE 0x00000026 +#define ISC_ENABLE 0x000008c6 +#define ISC_ERASE 0x0000040e +#define ISC_NOOP 0xffffffff +#define ISC_PROGRAMDONE 0x0000005e +#define LSC_CHECKBUSY 0x000000f0 +#define LSC_INITADDRESS 0x00000046 +#define LSC_PROGINCRNV 0x01000070 +#define LSC_REFRESH 0x00000079 + +#define BUSYFLAG BIT(7) + +/* + * Max CCLK in Slave SPI mode according to 'MachXO2 Family Data + * Sheet' sysCONFIG Port Timing Specifications (3-36) + */ +#define MACHXO2_MAX_SPEED 66000000 + +#define MACHXO2_LOW_DELAY 5 /* us */ +#define MACHXO2_HIGH_DELAY 200 /* us */ +#define MACHXO2_REFRESH 4800 /* us */ + +#define MACHXO2_OP_SIZE sizeof(u32) +#define MACHXO2_PAGE_SIZE 16 +#define MACHXO2_BUF_SIZE (MACHXO2_OP_SIZE + MACHXO2_PAGE_SIZE) + +static int wait_until_not_busy(struct spi_device *spi) +{ + struct spi_message msg; + struct spi_transfer rx, tx; + u32 checkbusy = LSC_CHECKBUSY; + u8 busy; + int ret; + + do { + memset(&rx, 0, sizeof(rx)); + memset(&tx, 0, sizeof(tx)); + tx.tx_buf = &checkbusy; + tx.len = MACHXO2_OP_SIZE; + rx.rx_buf = &busy; + rx.len = sizeof(busy); + spi_message_init(&msg); + spi_message_add_tail(&tx, &msg); + spi_message_add_tail(&rx, &msg); + ret = spi_sync(spi, &msg); + if (ret) + return ret; + } while (busy & BUSYFLAG); + + return 0; +} + +static enum fpga_mgr_states machxo2_spi_state(struct fpga_manager *mgr) +{ + return FPGA_MGR_STATE_UNKNOWN; +} + +static int machxo2_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + struct spi_device *spi = mgr->priv; + struct spi_message msg; + struct spi_transfer tx[5]; + u32 disable = ISC_DISABLE; + u32 bypass = ISC_NOOP; + u32 enable = ISC_ENABLE; + u32 erase = ISC_ERASE; + u32 initaddr = LSC_INITADDRESS; + int ret; + + if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { + dev_err(&mgr->dev, + "Partial reconfiguration is not supported\n"); + return -ENOTSUPP; + } + + memset(tx, 0, sizeof(tx)); + spi_message_init(&msg); + tx[0].tx_buf = &disable; + tx[0].len = MACHXO2_OP_SIZE - 1; + spi_message_add_tail(&tx[0], &msg); + + tx[1].tx_buf = &bypass; + tx[1].len = MACHXO2_OP_SIZE; + spi_message_add_tail(&tx[1], &msg); + ret = spi_sync(spi, &msg); + if (ret) + goto fail; + + ret = wait_until_not_busy(spi); + if (ret) + goto fail; + + spi_message_init(&msg); + tx[2].tx_buf = &enable; + tx[2].len = MACHXO2_OP_SIZE; + tx[2].delay_usecs = MACHXO2_LOW_DELAY; + spi_message_add_tail(&tx[2], &msg); + + tx[3].tx_buf = &erase; + tx[3].len = MACHXO2_OP_SIZE; + spi_message_add_tail(&tx[3], &msg); + ret = spi_sync(spi, &msg); + if (ret) + goto fail; + + ret = wait_until_not_busy(spi); + if (ret) + goto fail; + + spi_message_init(&msg); + tx[4].tx_buf = &initaddr; + tx[4].len = MACHXO2_OP_SIZE; + spi_message_add_tail(&tx[4], &msg); + ret = spi_sync(spi, &msg); + if (ret) + goto fail; + + return 0; + +fail: + dev_err(&mgr->dev, "Error during FPGA init.\n"); + return ret; +} + +static int machxo2_write(struct fpga_manager *mgr, const char *buf, + size_t count) +{ + struct spi_device *spi = mgr->priv; + struct spi_message msg; + struct spi_transfer tx; + u32 progincr = LSC_PROGINCRNV; + u8 payload[MACHXO2_BUF_SIZE]; + int i, ret; + + if (count % MACHXO2_PAGE_SIZE != 0) { + dev_err(&mgr->dev, "Malformed payload.\n"); + return -EINVAL; + } + + memcpy(payload, &progincr, MACHXO2_OP_SIZE); + for (i = 0; i < count; i += MACHXO2_PAGE_SIZE) { + memcpy(&payload[MACHXO2_OP_SIZE], &buf[i], MACHXO2_PAGE_SIZE); + memset(&tx, 0, sizeof(tx)); + spi_message_init(&msg); + tx.tx_buf = payload; + tx.len = MACHXO2_BUF_SIZE; + tx.delay_usecs = MACHXO2_HIGH_DELAY; + spi_message_add_tail(&tx, &msg); + ret = spi_sync(spi, &msg); + if (ret) { + dev_err(&mgr->dev, "Error loading the bitstream.\n"); + return ret; + } + } + + return 0; +} + +static int machxo2_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + struct spi_device *spi = mgr->priv; + struct spi_message msg; + struct spi_transfer tx[2]; + u32 progdone = ISC_PROGRAMDONE; + u32 refresh = LSC_REFRESH; + int ret; + + memset(tx, 0, sizeof(tx)); + spi_message_init(&msg); + tx[0].tx_buf = &progdone; + tx[0].len = MACHXO2_OP_SIZE; + spi_message_add_tail(&tx[0], &msg); + ret = spi_sync(spi, &msg); + if (ret) + goto fail; + + ret = wait_until_not_busy(spi); + if (ret) + goto fail; + + spi_message_init(&msg); + tx[1].tx_buf = &refresh; + tx[1].len = MACHXO2_OP_SIZE - 1; + tx[1].delay_usecs = MACHXO2_REFRESH; + spi_message_add_tail(&tx[1], &msg); + ret = spi_sync(spi, &msg); + if (ret) + goto fail; + + return 0; + +fail: + dev_err(&mgr->dev, "Refresh failed.\n"); + return ret; +} + +static const struct fpga_manager_ops machxo2_ops = { + .state = machxo2_spi_state, + .write_init = machxo2_write_init, + .write = machxo2_write, + .write_complete = machxo2_write_complete, +}; + +static int machxo2_spi_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + + if (spi->max_speed_hz > MACHXO2_MAX_SPEED) { + dev_err(dev, "Speed is too high\n"); + return -EINVAL; + } + + return fpga_mgr_register(dev, "Lattice MachXO2 SPI FPGA Manager", + &machxo2_ops, spi); +} + +static int machxo2_spi_remove(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + + fpga_mgr_unregister(dev); + + return 0; +} + +static const struct of_device_id of_match[] = { + { .compatible = "lattice,machxo2-slave-spi", }, + {} +}; +MODULE_DEVICE_TABLE(of, of_match); + +static const struct spi_device_id lattice_ids[] = { + { "machxo2-slave-spi", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(spi, lattice_ids); + +static struct spi_driver machxo2_spi_driver = { + .driver = { + .name = "machxo2-slave-spi", + .of_match_table = of_match_ptr(of_match), + }, + .probe = machxo2_spi_probe, + .remove = machxo2_spi_remove, + .id_table = lattice_ids, +}; + +module_spi_driver(machxo2_spi_driver) + +MODULE_AUTHOR("Paolo Pisati "); +MODULE_DESCRIPTION("Load Lattice FPGA firmware over SPI"); +MODULE_LICENSE("GPL v2");