From patchwork Fri Jan 20 00:12:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joshua Clayton X-Patchwork-Id: 9527145 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 974FC60459 for ; Fri, 20 Jan 2017 00:21:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 86FC028678 for ; Fri, 20 Jan 2017 00:21:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 77CEF2867F; Fri, 20 Jan 2017 00:21:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DC9F128678 for ; Fri, 20 Jan 2017 00:21:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753295AbdATAVh (ORCPT ); Thu, 19 Jan 2017 19:21:37 -0500 Received: from mail-pf0-f194.google.com ([209.85.192.194]:34068 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753047AbdATAVf (ORCPT ); Thu, 19 Jan 2017 19:21:35 -0500 Received: by mail-pf0-f194.google.com with SMTP id y143so4227222pfb.1; Thu, 19 Jan 2017 16:20:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=oRUoUQoyuUc1hwf6bo/GcM1g9F3qqx/M+kesOYW2qWo=; b=RPdaG2O/ylk9n92zl1xDXjmp1X7zv8BGr/onmJbltkY8L6WGsnjf2IqoN8DOTlDI2c AeoOGoDtjLZAzvU5XTetbb2oWvA1GS3Wn2qomflGKPEFQ1ZxNktzeWRRbA0Odu3fiBA0 vsYyUF3EsAR2GZaDqOugvwUBNiemEyfJyk+ZjFkpTxxHwF+V8U/o5wHZSlAuz++jhtPA VpAb1sYW7W/JcyH0gMG+aC08VssxHYoq5cH3JrI55qBAkBAh+ZjaSLA6x3xqLhWEH+RA vxbjFna3CDnVPOpBSyFRw8Cu2AhTw4pbAad32t55JwZwl8JGD0B3PUIxlH3LJj/u72Ha r7nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=oRUoUQoyuUc1hwf6bo/GcM1g9F3qqx/M+kesOYW2qWo=; b=VYhz+MdVILMWGSs/ZBeAZz7VkYG/gnGX+TkWkxXuhf6ioqGj3Lzlbhgqx7/E9GcKzW JgADfblkfybNhfxneMYAWaDtvl2I0VPD+5F+yjQ13WoF0zoLwZbL+c7ebWrw0CQe/vkl IZJpghq78YKdL7tE6eQRC4iil9XbXs2H+Sdhybb10Anu6MiVz4NWKU//fBeIuSM4cywm l/75a5oycFTIYNuRXXtgOUBHou4w3UIOuj5VUacokOZBCdYfQukVbsoPR0PNuc6iKqnc tfZiVtfhBDjZK+ijxqGmz/0jx2tKq7lhOzJCz1HQBeoq1nqBLpe2HXe5BVwQ1M4QQ+OY 3Gfw== X-Gm-Message-State: AIkVDXIQ8Ryp1n/RKwISkyY6732IirdoYEreqsCATPUrKmU8CCyltcH84PsSBIA/xV/gKQ== X-Received: by 10.98.111.194 with SMTP id k185mr12943600pfc.83.1484871161160; Thu, 19 Jan 2017 16:12:41 -0800 (PST) Received: from jclayton-pc.columbia.uniwest.com (68-185-59-186.static.knwc.wa.charter.com. [68.185.59.186]) by smtp.gmail.com with ESMTPSA id i10sm11438465pgd.37.2017.01.19.16.12.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jan 2017 16:12:40 -0800 (PST) From: Joshua Clayton To: Alan Tull , Moritz Fischer , Russell King , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Mark Rutland , Rob Herring , Anatolij Gustschin , Joshua Clayton , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-fpga@vger.kernel.org Subject: [PATCH v7 2/3] fpga manager: Add cyclone-ps-spi driver for Altera FPGAs Date: Thu, 19 Jan 2017 16:12:28 -0800 Message-Id: <1b85ccf11096b8ef6c3a9eee9e5897c27b89a825.1484869881.git.stillcompiling@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: In-Reply-To: References: Sender: linux-fpga-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial" interface on Altera Cyclone FPGAS. This is one of the simpler ways to set up an FPGA at runtime. The signal interface is close to unidirectional spi with lsb first. Signed-off-by: Joshua Clayton --- drivers/fpga/Kconfig | 7 ++ drivers/fpga/Makefile | 1 + drivers/fpga/cyclone-ps-spi.c | 185 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 193 insertions(+) create mode 100644 drivers/fpga/cyclone-ps-spi.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index ce861a2..e6c032d 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -20,6 +20,13 @@ config FPGA_REGION FPGA Regions allow loading FPGA images under control of the Device Tree. +config FPGA_MGR_CYCLONE_PS_SPI + tristate "Altera Cyclone FPGA Passive Serial over SPI" + depends on SPI + help + FPGA manager driver support for Altera Cyclone using the + passive serial interface over SPI + config FPGA_MGR_SOCFPGA tristate "Altera SOCFPGA FPGA Manager" depends on ARCH_SOCFPGA || COMPILE_TEST diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 8df07bc..a112bef 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_FPGA) += fpga-mgr.o # FPGA Manager Drivers +obj-$(CONFIG_FPGA_MGR_CYCLONE_PS_SPI) += cyclone-ps-spi.o obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o diff --git a/drivers/fpga/cyclone-ps-spi.c b/drivers/fpga/cyclone-ps-spi.c new file mode 100644 index 0000000..ae9c2c8 --- /dev/null +++ b/drivers/fpga/cyclone-ps-spi.c @@ -0,0 +1,185 @@ +/** + * Altera Cyclone Passive Serial SPI Driver + * + * Copyright (c) 2017 United Western Technologies, Corporation + * + * Joshua Clayton + * + * Manage Altera FPGA firmware that is loaded over spi using the passive + * serial configuration method. + * Firmware must be in binary "rbf" format. + * Works on Cyclone V. Should work on cyclone series. + * May work on other Altera FPGAs. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define FPGA_RESET_TIME 50 /* time in usecs to trigger FPGA config */ +#define FPGA_MIN_DELAY 50 /* min usecs to wait for config status */ +#define FPGA_MAX_DELAY 1000 /* max usecs to wait for config status */ + +struct cyclonespi_conf { + struct gpio_desc *config; + struct gpio_desc *status; + struct spi_device *spi; +}; + +static const struct of_device_id of_ef_match[] = { + { .compatible = "altr,fpga-passive-serial", }, + {} +}; +MODULE_DEVICE_TABLE(of, of_ef_match); + +static enum fpga_mgr_states cyclonespi_state(struct fpga_manager *mgr) +{ + struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv; + + if (gpiod_get_value(conf->status)) + return FPGA_MGR_STATE_RESET; + + return FPGA_MGR_STATE_UNKNOWN; +} + +static int cyclonespi_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv; + int i; + + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { + dev_err(&mgr->dev, "Partial reconfiguration not supported.\n"); + return -EINVAL; + } + + gpiod_set_value(conf->config, 1); + usleep_range(FPGA_RESET_TIME, FPGA_RESET_TIME + 20); + if (!gpiod_get_value(conf->status)) { + dev_err(&mgr->dev, "Status pin failed to show a reset\n"); + return -EIO; + } + + gpiod_set_value(conf->config, 0); + for (i = 0; i < (FPGA_MAX_DELAY / FPGA_MIN_DELAY); i++) { + usleep_range(FPGA_MIN_DELAY, FPGA_MIN_DELAY + 20); + if (!gpiod_get_value(conf->status)) + return 0; + } + + dev_err(&mgr->dev, "Status pin not ready.\n"); + return -EIO; +} + +static void rev_buf(char *buf, size_t len) +{ + const u8 *fw_end = (buf + len); + + /* set buffer to lsb first */ + while (buf < fw_end) { + *buf = bitrev8(*buf); + buf++; + } +} + +static int cyclonespi_write(struct fpga_manager *mgr, const char *buf, + size_t count) +{ + struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv; + const char *fw_data = buf; + const char *fw_data_end = fw_data + count; + + while (fw_data < fw_data_end) { + int ret; + size_t stride = min(fw_data_end - fw_data, SZ_4K); + + rev_buf(fw_data, stride); + ret = spi_write(conf->spi, fw_data, stride); + if (ret) { + dev_err(&mgr->dev, "spi error in firmware write: %d\n", + ret); + return ret; + } + fw_data += stride; + } + + return 0; +} + +static int cyclonespi_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + struct cyclonespi_conf *conf = (struct cyclonespi_conf *)mgr->priv; + + if (gpiod_get_value(conf->status)) { + dev_err(&mgr->dev, "Error during configuration.\n"); + return -EIO; + } + + return 0; +} + +static const struct fpga_manager_ops cyclonespi_ops = { + .state = cyclonespi_state, + .write_init = cyclonespi_write_init, + .write = cyclonespi_write, + .write_complete = cyclonespi_write_complete, +}; + +static int cyclonespi_probe(struct spi_device *spi) +{ + struct cyclonespi_conf *conf = devm_kzalloc(&spi->dev, sizeof(*conf), + GFP_KERNEL); + + if (!conf) + return -ENOMEM; + + conf->spi = spi; + conf->config = devm_gpiod_get(&spi->dev, "nconfig", GPIOD_OUT_HIGH); + if (IS_ERR(conf->config)) { + dev_err(&spi->dev, "Failed to get config gpio: %ld\n", + PTR_ERR(conf->config)); + return PTR_ERR(conf->config); + } + + conf->status = devm_gpiod_get(&spi->dev, "nstat", GPIOD_IN); + if (IS_ERR(conf->status)) { + dev_err(&spi->dev, "Failed to get status gpio: %ld\n", + PTR_ERR(conf->status)); + return PTR_ERR(conf->status); + } + + return fpga_mgr_register(&spi->dev, + "Altera Cyclone PS SPI FPGA Manager", + &cyclonespi_ops, conf); +} + +static int cyclonespi_remove(struct spi_device *spi) +{ + fpga_mgr_unregister(&spi->dev); + + return 0; +} + +static struct spi_driver cyclonespi_driver = { + .driver = { + .name = "cyclone-ps-spi", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(of_ef_match), + }, + .probe = cyclonespi_probe, + .remove = cyclonespi_remove, +}; + +module_spi_driver(cyclonespi_driver) + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Joshua Clayton "); +MODULE_DESCRIPTION("Module to load Altera FPGA firmware over spi");