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Wed, 24 Oct 2018 00:34:40 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1gFDgZ-0005zV-89; Wed, 24 Oct 2018 00:34:35 -0700 Received: from xsj-pvapsmtp01 (xsj-mail.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id w9O7YPF3009493; Wed, 24 Oct 2018 00:34:25 -0700 Received: from [172.23.37.118] (helo=xhdnavam40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1gFDgP-0005vF-2c; Wed, 24 Oct 2018 00:34:25 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , Subject: [PATCH v2 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver Date: Thu, 25 Oct 2018 13:02:05 +0530 Message-ID: <20181025073206.9264-3-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181025073206.9264-1-nava.manne@xilinx.com> References: <20181025073206.9264-1-nava.manne@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.100;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(396003)(346002)(39860400002)(136003)(376002)(2980300002)(438002)(189003)(199004)(39060400002)(47776003)(9786002)(478600001)(106002)(7696005)(356004)(36386004)(305945005)(106466001)(63266004)(50466002)(76176011)(476003)(51416003)(36756003)(126002)(11346002)(16586007)(316002)(77096007)(5660300001)(110136005)(446003)(2616005)(81156014)(186003)(426003)(336012)(8676002)(8936002)(81166006)(6666004)(486006)(1076002)(48376002)(2201001)(50226002)(2906002)(26005)(107986001)(921003)(5001870100001)(1121003)(83996005)(2101003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN4PR0201MB3519;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;LANG:en;PTR:xapps1.xilinx.com,unknown-60-100.xilinx.com;MX:1;A:1; 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Signed-off-by: Nava kishore Manne --- Changes for v2: -Removed "----" separators. Changes for v1: -Created a Seperate(New) DT binding file as suggested by Rob. Changes for RFC-V2: -Moved pcap node as a child to firwmare node as suggested by Rob. .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt new file mode 100644 index 000000000000..1f6f58872311 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt @@ -0,0 +1,13 @@ +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled +using ZynqMP SoC firmware interface +For Bitstream configuration on ZynqMp Soc uses processor configuration +port(PCAP) to configure the programmable logic(PL) through PS by using +FW interface. + +Required properties: +- compatible: should contain "xlnx,zynqmp-pcap-fpga" + +Example: + zynqmp_pcap: pcap { + compatible = "xlnx,zynqmp-pcap-fpga"; + };