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Tue, 26 Mar 2019 07:32:11 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1h8n7W-0003EX-5M; Tue, 26 Mar 2019 07:32:06 -0700 Received: from xsj-pvapsmtp01 (smtp3.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x2QEVxYj009375; Tue, 26 Mar 2019 07:32:00 -0700 Received: from [172.23.37.118] (helo=xhdnavam40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1h8n7P-0002t5-CQ; Tue, 26 Mar 2019 07:31:59 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , Subject: [PATCH v5 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver Date: Tue, 26 Mar 2019 20:01:29 +0530 Message-ID: <20190326143129.2608-7-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190326143129.2608-1-nava.manne@xilinx.com> References: <20190326143129.2608-1-nava.manne@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(346002)(396003)(376002)(136003)(39860400002)(2980300002)(199004)(189003)(5660300002)(8936002)(106466001)(50226002)(106002)(47776003)(2201001)(478600001)(36386004)(63266004)(48376002)(50466002)(2906002)(9786002)(305945005)(1076003)(76176011)(51416003)(7696005)(110136005)(316002)(16586007)(446003)(6666004)(63350400001)(63370400001)(81156014)(81166006)(426003)(8676002)(356004)(336012)(36756003)(2616005)(11346002)(486006)(126002)(476003)(77096007)(186003)(26005)(921003)(1121003)(83996005)(2101003);DIR:OUT;SFP:1101;SCL:1;SRVR:BLUSPR8PMB96;H:xsj-pvapsmtpgw01;FPR:;SPF:TempError;LANG:en;PTR:unknown-60-83.xilinx.com;A:1;MX:1; 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Signed-off-by: Nava kishore Manne Reviewed-by: Rob Herring Acked-by: Alan Tull Acked-by: Moritz Fischer --- Changes for v5: -Moved pcap node as a child to firwmare node as suggested by Rob. Changes for v4: -Modified binding description as suggested by Moritz Fischer. Changes for v3: -Removed PCAP as a child node to the FW and Created an independent node since PCAP driver is a consumer not a provider. .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt new file mode 100644 index 000000000000..3052bf619dd5 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt @@ -0,0 +1,25 @@ +Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager. +The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the +Programmable Logic (PL). The configuration uses the firmware interface. + +Required properties: +- compatible: should contain "xlnx,zynqmp-pcap-fpga" + +Example for full FPGA configuration: + + fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&zynqmp_pcap>; + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + + firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + zynqmp_pcap: pcap { + compatible = "xlnx,zynqmp-pcap-fpga"; + }; + }; + };