| Message ID | 20201114005559.90860-7-russell.h.weight@intel.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Intel MAX10 BMC Secure Update Driver | expand |
On 11/13/20 4:55 PM, Russ Weight wrote: > Extend the MAX10 BMC Secure Update driver to include > a function that returns 64 bits of additional HW specific > data for errors that require additional information. > This callback function enables the hw_errinfo sysfs > node in the Intel Security Manager class driver. > > Signed-off-by: Russ Weight <russell.h.weight@intel.com> > --- > v5: > - No change > v4: > - No change > v3: > - Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_ > - Changed "MAX10 BMC Secure Engine driver" to "MAX10 BMC Secure Update > driver" > v2: > - Implemented HW_ERRINFO_POISON for m10bmc_sec_hw_errinfo() to > ensure that corresponding bits are set to 1 if we are unable > to read the doorbell or auth_result registers. > - Added m10bmc_ prefix to functions in m10bmc_iops structure > --- > drivers/fpga/intel-m10-bmc-secure.c | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/drivers/fpga/intel-m10-bmc-secure.c b/drivers/fpga/intel-m10-bmc-secure.c > index 4fa8a2256088..a024efb173d3 100644 > --- a/drivers/fpga/intel-m10-bmc-secure.c > +++ b/drivers/fpga/intel-m10-bmc-secure.c > @@ -472,11 +472,36 @@ static enum fpga_sec_err m10bmc_sec_cancel(struct fpga_sec_mgr *smgr) > return ret ? FPGA_SEC_ERR_RW_ERROR : FPGA_SEC_ERR_NONE; > } > > +#define HW_ERRINFO_POISON GENMASK(31, 0) > +static u64 m10bmc_sec_hw_errinfo(struct fpga_sec_mgr *smgr) > +{ > + struct m10bmc_sec *sec = smgr->priv; > + u32 doorbell, auth_result; If doorbell and auth_result were poisoned at initialization, the if-checks could be skipped. Tom > + > + switch (smgr->err_code) { > + case FPGA_SEC_ERR_HW_ERROR: > + case FPGA_SEC_ERR_TIMEOUT: > + case FPGA_SEC_ERR_BUSY: > + case FPGA_SEC_ERR_WEAROUT: > + if (m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell)) > + doorbell = HW_ERRINFO_POISON; > + > + if (m10bmc_sys_read(sec->m10bmc, M10BMC_AUTH_RESULT, > + &auth_result)) > + auth_result = HW_ERRINFO_POISON; > + > + return (u64)doorbell << 32 | (u64)auth_result; > + default: > + return 0; > + } > +} > + > static const struct fpga_sec_mgr_ops m10bmc_sops = { > .prepare = m10bmc_sec_prepare, > .write_blk = m10bmc_sec_write_blk, > .poll_complete = m10bmc_sec_poll_complete, > .cancel = m10bmc_sec_cancel, > + .get_hw_errinfo = m10bmc_sec_hw_errinfo, > }; > > static int m10bmc_secure_probe(struct platform_device *pdev)
On 11/15/20 6:20 AM, Tom Rix wrote: > On 11/13/20 4:55 PM, Russ Weight wrote: >> Extend the MAX10 BMC Secure Update driver to include >> a function that returns 64 bits of additional HW specific >> data for errors that require additional information. >> This callback function enables the hw_errinfo sysfs >> node in the Intel Security Manager class driver. >> >> Signed-off-by: Russ Weight <russell.h.weight@intel.com> >> --- >> v5: >> - No change >> v4: >> - No change >> v3: >> - Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_ >> - Changed "MAX10 BMC Secure Engine driver" to "MAX10 BMC Secure Update >> driver" >> v2: >> - Implemented HW_ERRINFO_POISON for m10bmc_sec_hw_errinfo() to >> ensure that corresponding bits are set to 1 if we are unable >> to read the doorbell or auth_result registers. >> - Added m10bmc_ prefix to functions in m10bmc_iops structure >> --- >> drivers/fpga/intel-m10-bmc-secure.c | 25 +++++++++++++++++++++++++ >> 1 file changed, 25 insertions(+) >> >> diff --git a/drivers/fpga/intel-m10-bmc-secure.c b/drivers/fpga/intel-m10-bmc-secure.c >> index 4fa8a2256088..a024efb173d3 100644 >> --- a/drivers/fpga/intel-m10-bmc-secure.c >> +++ b/drivers/fpga/intel-m10-bmc-secure.c >> @@ -472,11 +472,36 @@ static enum fpga_sec_err m10bmc_sec_cancel(struct fpga_sec_mgr *smgr) >> return ret ? FPGA_SEC_ERR_RW_ERROR : FPGA_SEC_ERR_NONE; >> } >> >> +#define HW_ERRINFO_POISON GENMASK(31, 0) >> +static u64 m10bmc_sec_hw_errinfo(struct fpga_sec_mgr *smgr) >> +{ >> + struct m10bmc_sec *sec = smgr->priv; >> + u32 doorbell, auth_result; > If doorbell and auth_result were poisoned at initialization, the if-checks could be skipped. Yes - I'll make this change. - Russ > > Tom > >> + >> + switch (smgr->err_code) { >> + case FPGA_SEC_ERR_HW_ERROR: >> + case FPGA_SEC_ERR_TIMEOUT: >> + case FPGA_SEC_ERR_BUSY: >> + case FPGA_SEC_ERR_WEAROUT: >> + if (m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell)) >> + doorbell = HW_ERRINFO_POISON; >> + >> + if (m10bmc_sys_read(sec->m10bmc, M10BMC_AUTH_RESULT, >> + &auth_result)) >> + auth_result = HW_ERRINFO_POISON; >> + >> + return (u64)doorbell << 32 | (u64)auth_result; >> + default: >> + return 0; >> + } >> +} >> + >> static const struct fpga_sec_mgr_ops m10bmc_sops = { >> .prepare = m10bmc_sec_prepare, >> .write_blk = m10bmc_sec_write_blk, >> .poll_complete = m10bmc_sec_poll_complete, >> .cancel = m10bmc_sec_cancel, >> + .get_hw_errinfo = m10bmc_sec_hw_errinfo, >> }; >> >> static int m10bmc_secure_probe(struct platform_device *pdev)
diff --git a/drivers/fpga/intel-m10-bmc-secure.c b/drivers/fpga/intel-m10-bmc-secure.c index 4fa8a2256088..a024efb173d3 100644 --- a/drivers/fpga/intel-m10-bmc-secure.c +++ b/drivers/fpga/intel-m10-bmc-secure.c @@ -472,11 +472,36 @@ static enum fpga_sec_err m10bmc_sec_cancel(struct fpga_sec_mgr *smgr) return ret ? FPGA_SEC_ERR_RW_ERROR : FPGA_SEC_ERR_NONE; } +#define HW_ERRINFO_POISON GENMASK(31, 0) +static u64 m10bmc_sec_hw_errinfo(struct fpga_sec_mgr *smgr) +{ + struct m10bmc_sec *sec = smgr->priv; + u32 doorbell, auth_result; + + switch (smgr->err_code) { + case FPGA_SEC_ERR_HW_ERROR: + case FPGA_SEC_ERR_TIMEOUT: + case FPGA_SEC_ERR_BUSY: + case FPGA_SEC_ERR_WEAROUT: + if (m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell)) + doorbell = HW_ERRINFO_POISON; + + if (m10bmc_sys_read(sec->m10bmc, M10BMC_AUTH_RESULT, + &auth_result)) + auth_result = HW_ERRINFO_POISON; + + return (u64)doorbell << 32 | (u64)auth_result; + default: + return 0; + } +} + static const struct fpga_sec_mgr_ops m10bmc_sops = { .prepare = m10bmc_sec_prepare, .write_blk = m10bmc_sec_write_blk, .poll_complete = m10bmc_sec_poll_complete, .cancel = m10bmc_sec_cancel, + .get_hw_errinfo = m10bmc_sec_hw_errinfo, }; static int m10bmc_secure_probe(struct platform_device *pdev)
Extend the MAX10 BMC Secure Update driver to include a function that returns 64 bits of additional HW specific data for errors that require additional information. This callback function enables the hw_errinfo sysfs node in the Intel Security Manager class driver. Signed-off-by: Russ Weight <russell.h.weight@intel.com> --- v5: - No change v4: - No change v3: - Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_ - Changed "MAX10 BMC Secure Engine driver" to "MAX10 BMC Secure Update driver" v2: - Implemented HW_ERRINFO_POISON for m10bmc_sec_hw_errinfo() to ensure that corresponding bits are set to 1 if we are unable to read the doorbell or auth_result registers. - Added m10bmc_ prefix to functions in m10bmc_iops structure --- drivers/fpga/intel-m10-bmc-secure.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)