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Fri, 2 Apr 2021 02:28:54 -0700 Envelope-to: git@xilinx.com, mdf@kernel.org, trix@redhat.com, robh+dt@kernel.org, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Received: from [10.140.6.60] (port=58326 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lSG6m-0005gX-ST; Fri, 02 Apr 2021 02:28:53 -0700 From: Nava kishore Manne To: , , , , , , , , , Subject: [PATCH 3/3] fpga: region: Adds runtime PM support Date: Fri, 2 Apr 2021 14:50:49 +0530 Message-ID: <20210402092049.479-4-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210402092049.479-1-nava.manne@xilinx.com> References: <20210402092049.479-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1c3bd0c6-dff7-4fc8-d98d-08d8f5b9be0d X-MS-TrafficTypeDiagnostic: BL0PR02MB5697: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:3044; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2021 09:28:57.8449 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c3bd0c6-dff7-4fc8-d98d-08d8f5b9be0d X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT006.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR02MB5697 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Adds support to handle FPGA/PL power domain. With this patch, the PL power domain will be turned on before loading the bitstream and turned off while removing/unloading the bitstream using overlays. This can be achieved by adding the runtime PM support. Signed-off-by: Nava kishore Manne --- drivers/fpga/of-fpga-region.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c index e405309baadc..35fc2f3d4bd8 100644 --- a/drivers/fpga/of-fpga-region.c +++ b/drivers/fpga/of-fpga-region.c @@ -15,6 +15,7 @@ #include #include #include +#include static const struct of_device_id fpga_region_of_match[] = { { .compatible = "fpga-region", }, @@ -302,6 +303,7 @@ static int of_fpga_region_notify_pre_apply(struct fpga_region *region, } region->info = info; + pm_runtime_get_sync(dev->parent); ret = fpga_region_program_fpga(region); if (ret) { /* error; reject overlay */ @@ -324,10 +326,13 @@ static int of_fpga_region_notify_pre_apply(struct fpga_region *region, static void of_fpga_region_notify_post_remove(struct fpga_region *region, struct of_overlay_notify_data *nd) { + struct device *dev = ®ion->dev; + fpga_bridges_disable(®ion->bridge_list); fpga_bridges_put(®ion->bridge_list); fpga_image_info_free(region->info); region->info = NULL; + pm_runtime_put(dev->parent); } /** @@ -411,9 +416,16 @@ static int of_fpga_region_probe(struct platform_device *pdev) goto eprobe_mgr_put; } + pm_runtime_enable(&pdev->dev); + ret = pm_runtime_get_sync(&pdev->dev); + if (ret < 0) + goto err_pm; + + pm_runtime_put(&pdev->dev); + ret = fpga_region_register(region); if (ret) - goto eprobe_mgr_put; + goto err_pm; of_platform_populate(np, fpga_region_of_match, NULL, ®ion->dev); platform_set_drvdata(pdev, region); @@ -422,6 +434,9 @@ static int of_fpga_region_probe(struct platform_device *pdev) return 0; +err_pm: + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); eprobe_mgr_put: fpga_mgr_put(mgr); return ret; @@ -434,6 +449,7 @@ static int of_fpga_region_remove(struct platform_device *pdev) fpga_region_unregister(region); fpga_mgr_put(mgr); + pm_runtime_disable(region->dev.parent); return 0; }