From patchwork Mon May 3 21:40:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russ Weight X-Patchwork-Id: 12237087 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8871C43460 for ; Mon, 3 May 2021 21:40:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B28C861283 for ; Mon, 3 May 2021 21:40:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229771AbhECVln (ORCPT ); Mon, 3 May 2021 17:41:43 -0400 Received: from mga11.intel.com ([192.55.52.93]:49664 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229742AbhECVlm (ORCPT ); Mon, 3 May 2021 17:41:42 -0400 IronPort-SDR: mIscvnMa11oWX/BxbnUFJ4cXu44doN3bM+TnIQFmhVu/k3C/DFBLjEu5NC/LUblRDe1oW9LYjE OU7cI3nhoaVA== X-IronPort-AV: E=McAfee;i="6200,9189,9973"; a="194699865" X-IronPort-AV: E=Sophos;i="5.82,271,1613462400"; d="scan'208";a="194699865" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2021 14:40:47 -0700 IronPort-SDR: DQy5a5gvHp+h5LqMG8/xEtWav4end5s8cQm6oDBf8ijROvwoGyOmvruhWFsAZ1fM0AihFc2xWD x2LvPl8FoKZw== X-IronPort-AV: E=Sophos;i="5.82,271,1613462400"; d="scan'208";a="538933123" Received: from rhweight-mobl2.amr.corp.intel.com (HELO rhweight-mobl2.ra.intel.com) ([10.212.218.202]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2021 14:40:47 -0700 From: Russ Weight To: mdf@kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: trix@redhat.com, lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com, matthew.gerlach@intel.com, richard.gong@intel.com, Russ Weight Subject: [PATCH v12 5/5] fpga: m10bmc-sec: add max10 get_hw_errinfo callback func Date: Mon, 3 May 2021 14:40:42 -0700 Message-Id: <20210503214042.316836-6-russell.h.weight@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210503214042.316836-1-russell.h.weight@intel.com> References: <20210503214042.316836-1-russell.h.weight@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Extend the MAX10 BMC Secure Update driver to include a function that returns 64 bits of additional HW specific data for errors that require additional information. This callback function enables the hw_errinfo sysfs node in the Intel Security Manager class driver. Signed-off-by: Russ Weight Reviewed-by: Tom Rix --- v12: - No change v11: - No change v10: - No change v9: - No change v8: - Previously patch 6/6, otherwise no change v7: - No change v6: - Initialized auth_result and doorbell to HW_ERRINFO_POISON in m10bmc_sec_hw_errinfo() and removed unnecessary if statements. v5: - No change v4: - No change v3: - Changed: iops -> sops, imgr -> smgr, IFPGA_ -> FPGA_, ifpga_ to fpga_ - Changed "MAX10 BMC Secure Engine driver" to "MAX10 BMC Secure Update driver" v2: - Implemented HW_ERRINFO_POISON for m10bmc_sec_hw_errinfo() to ensure that corresponding bits are set to 1 if we are unable to read the doorbell or auth_result registers. - Added m10bmc_ prefix to functions in m10bmc_iops structure --- drivers/fpga/intel-m10-bmc-secure.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/fpga/intel-m10-bmc-secure.c b/drivers/fpga/intel-m10-bmc-secure.c index 9d45312001a3..bdf87ec125fe 100644 --- a/drivers/fpga/intel-m10-bmc-secure.c +++ b/drivers/fpga/intel-m10-bmc-secure.c @@ -483,11 +483,33 @@ static enum fpga_sec_err m10bmc_sec_cancel(struct fpga_sec_mgr *smgr) return ret ? FPGA_SEC_ERR_RW_ERROR : FPGA_SEC_ERR_NONE; } +#define HW_ERRINFO_POISON GENMASK(31, 0) +static u64 m10bmc_sec_hw_errinfo(struct fpga_sec_mgr *smgr) +{ + struct m10bmc_sec *sec = smgr->priv; + u32 auth_result = HW_ERRINFO_POISON; + u32 doorbell = HW_ERRINFO_POISON; + + switch (smgr->err_code) { + case FPGA_SEC_ERR_HW_ERROR: + case FPGA_SEC_ERR_TIMEOUT: + case FPGA_SEC_ERR_BUSY: + case FPGA_SEC_ERR_WEAROUT: + m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell); + m10bmc_sys_read(sec->m10bmc, M10BMC_AUTH_RESULT, &auth_result); + + return (u64)doorbell << 32 | (u64)auth_result; + default: + return 0; + } +} + static const struct fpga_sec_mgr_ops m10bmc_sops = { .prepare = m10bmc_sec_prepare, .write_blk = m10bmc_sec_write_blk, .poll_complete = m10bmc_sec_poll_complete, .cancel = m10bmc_sec_cancel, + .get_hw_errinfo = m10bmc_sec_hw_errinfo, }; static int m10bmc_secure_probe(struct platform_device *pdev)