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Wed, 12 May 2021 05:51:17 -0700 Envelope-to: git@xilinx.com, robh+dt@kernel.org, mdf@kernel.org, trix@redhat.com, arnd@arndb.de, gregkh@linuxfoundation.org, zou_wei@huawei.com, iwamatsu@nigauri.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org, chinnikishore369@gmail.com Received: from [10.140.6.60] (port=37340 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lgoKZ-0002rt-MH; Wed, 12 May 2021 05:51:16 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , , , , , , CC: Appana Durga Kedareswara rao Subject: [PATCH v5 4/4] fpga: versal-fpga: Add versal fpga manager driver Date: Wed, 12 May 2021 18:20:42 +0530 Message-ID: <20210512125042.30973-5-nava.manne@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210512125042.30973-1-nava.manne@xilinx.com> References: <20210512125042.30973-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 61169f0b-341c-4736-e879-08d91544aa83 X-MS-TrafficTypeDiagnostic: BN6PR02MB2772: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2021 12:51:31.1467 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 61169f0b-341c-4736-e879-08d91544aa83 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: DM3NAM02FT028.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB2772 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Add support for Xilinx Versal FPGA manager. PDI source type can be DDR, OCM, QSPI flash etc.. But driver allocates memory always from DDR, Since driver supports only DDR source type. Signed-off-by: Appana Durga Kedareswara rao Signed-off-by: Nava kishore Manne --- Changes for v2: -Updated the Fpga Mgr registrations call's to 5.11 -Fixed some minor coding issues as suggested by Moritz. Changes for v3: -Rewritten the Versal fpga Kconfig contents. Changes for v4: -Rebased the changes on linux-next. No functional changes. Changes for v5: -None. drivers/fpga/Kconfig | 9 +++ drivers/fpga/Makefile | 1 + drivers/fpga/versal-fpga.c | 117 +++++++++++++++++++++++++++++++++++++ 3 files changed, 127 insertions(+) create mode 100644 drivers/fpga/versal-fpga.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 33e15058d0dc..92c20b92357a 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -234,4 +234,13 @@ config FPGA_MGR_ZYNQMP_FPGA to configure the programmable logic(PL) through PS on ZynqMP SoC. +config FPGA_MGR_VERSAL_FPGA + tristate "Xilinx Versal FPGA" + depends on ARCH_ZYNQMP || COMPILE_TEST + help + Select this option to enable FPGA manager driver support for + Xilinx Versal SoC. This driver uses the firmware interface to + configure the programmable logic(PL). + + To compile this as a module, choose M here. endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 18dc9885883a..0bff783d1b61 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c new file mode 100644 index 000000000000..5744e44f981d --- /dev/null +++ b/drivers/fpga/versal-fpga.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2021 Xilinx, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * struct versal_fpga_priv - Private data structure + * @dev: Device data structure + */ +struct versal_fpga_priv { + struct device *dev; +}; + +static int versal_fpga_ops_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t size) +{ + return 0; +} + +static int versal_fpga_ops_write(struct fpga_manager *mgr, + const char *buf, size_t size) +{ + struct versal_fpga_priv *priv; + dma_addr_t dma_addr = 0; + char *kbuf; + int ret; + + priv = mgr->priv; + + kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); + if (!kbuf) + return -ENOMEM; + + memcpy(kbuf, buf, size); + + wmb(); /* ensure all writes are done before initiate FW call */ + + ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr); + + dma_free_coherent(priv->dev, size, kbuf, dma_addr); + + return ret; +} + +static int versal_fpga_ops_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + return 0; +} + +static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr) +{ + return FPGA_MGR_STATE_UNKNOWN; +} + +static const struct fpga_manager_ops versal_fpga_ops = { + .state = versal_fpga_ops_state, + .write_init = versal_fpga_ops_write_init, + .write = versal_fpga_ops_write, + .write_complete = versal_fpga_ops_write_complete, +}; + +static int versal_fpga_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct versal_fpga_priv *priv; + struct fpga_manager *mgr; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (ret < 0) { + dev_err(dev, "no usable DMA configuration\n"); + return ret; + } + + mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager", + &versal_fpga_ops, priv); + if (!mgr) + return -ENOMEM; + + return devm_fpga_mgr_register(dev, mgr); +} + +static const struct of_device_id versal_fpga_of_match[] = { + { .compatible = "xlnx,versal-fpga", }, + {}, +}; +MODULE_DEVICE_TABLE(of, versal_fpga_of_match); + +static struct platform_driver versal_fpga_driver = { + .probe = versal_fpga_probe, + .driver = { + .name = "versal_fpga_manager", + .of_match_table = of_match_ptr(versal_fpga_of_match), + }, +}; +module_platform_driver(versal_fpga_driver); + +MODULE_AUTHOR("Nava kishore Manne "); +MODULE_AUTHOR("Appana Durga Kedareswara rao "); +MODULE_DESCRIPTION("Xilinx Versal FPGA Manager"); +MODULE_LICENSE("GPL");