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Thu, 27 May 2021 17:53:08 -0700 Envelope-to: mdf@kernel.org, robh@kernel.org, trix@redhat.com, devicetree@vger.kernel.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Received: from [172.19.73.109] (port=34036 helo=xsj-xw9400.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lmQkO-0003fY-66; Thu, 27 May 2021 17:53:08 -0700 Received: by xsj-xw9400.xilinx.com (Postfix, from userid 21952) id 1BAEE6032B1; Thu, 27 May 2021 17:50:07 -0700 (PDT) From: Lizhi Hou To: CC: Lizhi Hou , , , , , , , , , , , Max Zhen Subject: [PATCH V7 XRT Alveo 15/20] fpga: xrt: devctl xrt driver Date: Thu, 27 May 2021 17:49:54 -0700 Message-ID: <20210528004959.61354-16-lizhi.hou@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210528004959.61354-1-lizhi.hou@xilinx.com> References: <20210528004959.61354-1-lizhi.hou@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fef0c6bf-03df-44ab-ec04-08d92172f7d8 X-MS-TrafficTypeDiagnostic: BY5PR02MB6017: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:765; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2021 00:53:11.6403 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fef0c6bf-03df-44ab-ec04-08d92172f7d8 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT016.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR02MB6017 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Add devctl driver. devctl is a type of hardware function which only has few registers to read or write. They are discovered by walking firmware metadata. A xrt device node will be created for them. Signed-off-by: Sonal Santan Signed-off-by: Max Zhen Signed-off-by: Lizhi Hou Reviewed-by: Tom Rix --- drivers/fpga/xrt/include/xleaf/devctl.h | 40 ++++++ drivers/fpga/xrt/lib/xleaf/devctl.c | 169 ++++++++++++++++++++++++ 2 files changed, 209 insertions(+) create mode 100644 drivers/fpga/xrt/include/xleaf/devctl.h create mode 100644 drivers/fpga/xrt/lib/xleaf/devctl.c diff --git a/drivers/fpga/xrt/include/xleaf/devctl.h b/drivers/fpga/xrt/include/xleaf/devctl.h new file mode 100644 index 000000000000..b97f3b6d9326 --- /dev/null +++ b/drivers/fpga/xrt/include/xleaf/devctl.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + */ + +#ifndef _XRT_DEVCTL_H_ +#define _XRT_DEVCTL_H_ + +#include "xleaf.h" + +/* + * DEVCTL driver leaf calls. + */ +enum xrt_devctl_leaf_cmd { + XRT_DEVCTL_READ = XRT_XLEAF_CUSTOM_BASE, /* See comments in xleaf.h */ +}; + +enum xrt_devctl_id { + XRT_DEVCTL_ROM_UUID = 0, + XRT_DEVCTL_DDR_CALIB, + XRT_DEVCTL_GOLDEN_VER, + XRT_DEVCTL_MAX +}; + +struct xrt_devctl_rw { + u32 xdr_id; + void *xdr_buf; + u32 xdr_len; + u32 xdr_offset; +}; + +struct xrt_devctl_intf_uuid { + u32 uuid_num; + uuid_t *uuids; +}; + +#endif /* _XRT_DEVCTL_H_ */ diff --git a/drivers/fpga/xrt/lib/xleaf/devctl.c b/drivers/fpga/xrt/lib/xleaf/devctl.c new file mode 100644 index 000000000000..fb2122be7e56 --- /dev/null +++ b/drivers/fpga/xrt/lib/xleaf/devctl.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Alveo FPGA devctl Driver + * + * Copyright (C) 2020-2021 Xilinx, Inc. + * + * Authors: + * Lizhi Hou + */ + +#include +#include +#include +#include +#include +#include "metadata.h" +#include "xleaf.h" +#include "xleaf/devctl.h" + +#define XRT_DEVCTL "xrt_devctl" + +struct xrt_name_id { + char *ep_name; + int id; +}; + +static struct xrt_name_id name_id[XRT_DEVCTL_MAX] = { + { XRT_MD_NODE_BLP_ROM, XRT_DEVCTL_ROM_UUID }, + { XRT_MD_NODE_GOLDEN_VER, XRT_DEVCTL_GOLDEN_VER }, +}; + +XRT_DEFINE_REGMAP_CONFIG(devctl_regmap_config); + +struct xrt_devctl { + struct xrt_device *xdev; + struct regmap *regmap[XRT_DEVCTL_MAX]; + ulong sizes[XRT_DEVCTL_MAX]; +}; + +static int xrt_devctl_name2id(struct xrt_devctl *devctl, const char *name) +{ + int i; + + for (i = 0; i < XRT_DEVCTL_MAX && name_id[i].ep_name; i++) { + if (!strncmp(name_id[i].ep_name, name, strlen(name_id[i].ep_name) + 1)) + return name_id[i].id; + } + + return -EINVAL; +} + +static int +xrt_devctl_leaf_call(struct xrt_device *xdev, u32 cmd, void *arg) +{ + struct xrt_devctl *devctl; + int ret = 0; + + devctl = xrt_get_drvdata(xdev); + + switch (cmd) { + case XRT_XLEAF_EVENT: + /* Does not handle any event. */ + break; + case XRT_DEVCTL_READ: { + struct xrt_devctl_rw *rw_arg = arg; + + if (rw_arg->xdr_len & 0x3) { + xrt_err(xdev, "invalid len %d", rw_arg->xdr_len); + return -EINVAL; + } + + if (rw_arg->xdr_id >= XRT_DEVCTL_MAX) { + xrt_err(xdev, "invalid id %d", rw_arg->xdr_id); + return -EINVAL; + } + + if (!devctl->regmap[rw_arg->xdr_id]) { + xrt_err(xdev, "io not found, id %d", + rw_arg->xdr_id); + return -EINVAL; + } + + ret = regmap_bulk_read(devctl->regmap[rw_arg->xdr_id], rw_arg->xdr_offset, + rw_arg->xdr_buf, + rw_arg->xdr_len / devctl_regmap_config.reg_stride); + break; + } + default: + xrt_err(xdev, "unsupported cmd %d", cmd); + return -EINVAL; + } + + return ret; +} + +static int xrt_devctl_probe(struct xrt_device *xdev) +{ + struct xrt_devctl *devctl = NULL; + void __iomem *base = NULL; + struct resource *res; + int i, id, ret = 0; + + devctl = devm_kzalloc(&xdev->dev, sizeof(*devctl), GFP_KERNEL); + if (!devctl) + return -ENOMEM; + + devctl->xdev = xdev; + xrt_set_drvdata(xdev, devctl); + + xrt_info(xdev, "probing..."); + for (i = 0, res = xrt_get_resource(xdev, IORESOURCE_MEM, 0); + res; + res = xrt_get_resource(xdev, IORESOURCE_MEM, ++i)) { + struct regmap_config config = devctl_regmap_config; + + id = xrt_devctl_name2id(devctl, res->name); + if (id < 0) { + xrt_err(xdev, "ep %s not found", res->name); + continue; + } + base = devm_ioremap_resource(&xdev->dev, res); + if (IS_ERR(base)) { + ret = PTR_ERR(base); + break; + } + config.max_register = res->end - res->start + 1; + devctl->regmap[id] = devm_regmap_init_mmio(&xdev->dev, base, &config); + if (IS_ERR(devctl->regmap[id])) { + xrt_err(xdev, "map base failed %pR", res); + ret = PTR_ERR(devctl->regmap[id]); + break; + } + devctl->sizes[id] = res->end - res->start + 1; + } + + return ret; +} + +static struct xrt_dev_endpoints xrt_devctl_endpoints[] = { + { + .xse_names = (struct xrt_dev_ep_names[]) { + /* add name if ep is in same partition */ + { .ep_name = XRT_MD_NODE_BLP_ROM }, + { NULL }, + }, + .xse_min_ep = 1, + }, + { + .xse_names = (struct xrt_dev_ep_names[]) { + { .ep_name = XRT_MD_NODE_GOLDEN_VER }, + { NULL }, + }, + .xse_min_ep = 1, + }, + /* adding ep bundle generates devctl device instance */ + { 0 }, +}; + +static struct xrt_driver xrt_devctl_driver = { + .driver = { + .name = XRT_DEVCTL, + }, + .subdev_id = XRT_SUBDEV_DEVCTL, + .endpoints = xrt_devctl_endpoints, + .probe = xrt_devctl_probe, + .leaf_call = xrt_devctl_leaf_call, +}; + +XRT_LEAF_INIT_FINI_FUNC(devctl);