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[V3,XRT,Alveo,Infrastructure,2/8] Documentation: devicetree: bindings: add xrt group binding

Message ID 20211204003957.1448567-3-lizhi.hou@xilinx.com (mailing list archive)
State New
Headers show
Series XRT Alveo driver infrastructure overview | expand

Commit Message

Lizhi Hou Dec. 4, 2021, 12:39 a.m. UTC 
Create device tree binding document for xrt group device.

Signed-off-by: Sonal Santan <sonal.santan@xilinx.com>
Signed-off-by: Max Zhen <max.zhen@xilinx.com>
Signed-off-by: Lizhi Hou <lizhi.hou@xilinx.com>
---
 .../bindings/xrt/xlnx,xrt-group.yaml          | 57 +++++++++++++++++++
 1 file changed, 57 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/xrt/xlnx,xrt-group.yaml
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Patch

diff --git a/Documentation/devicetree/bindings/xrt/xlnx,xrt-group.yaml b/Documentation/devicetree/bindings/xrt/xlnx,xrt-group.yaml
new file mode 100644
index 000000000000..6cc7a83d7c14
--- /dev/null
+++ b/Documentation/devicetree/bindings/xrt/xlnx,xrt-group.yaml
@@ -0,0 +1,57 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/xrt/xlnx,xrt-group.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx XRT group for Alveo platforms
+
+description: |
+  The xrt group is a pseudo device which is used to manage and
+  support xrt devices in the same Alveo partition. It is part
+  of XRT infrastructure.
+
+maintainers:
+  - Lizhi Hou <lizhi.hou@xilinx.com>
+
+properties:
+  compatible:
+    const: xlnx,xrt-group
+
+  "#address-cells":
+    const: 3
+
+  "#size-cells":
+    const: 2
+
+  ranges: true
+
+patternProperties:
+  "^.*@[0-5],[0-9a-f]+,[0-9a-f]+$":
+    description: xrt devices belongs to this group
+    type: object
+
+required:
+  - compatible
+  - "#address-cells"
+  - "#size-cells"
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    xrt-bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        xrt-group@48,0 {
+            compatible = "xlnx,xrt-group";
+            #address-cells = <3>;
+            #size-cells = <2>;
+            ranges = <0 0 0 0 0xe0000000 0 0x2000000
+                      2 0 0 0 0xe4200000 0 0x40000>;
+            ep_fpga_configuration_00@0,0,1e88000 {
+                reg = <0 0 0x1e88000 0 0x8000>;
+            };
+        };
+    };