From patchwork Thu Feb 24 09:22:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 12758206 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34BDFC433EF for ; Thu, 24 Feb 2022 09:27:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232417AbiBXJ00 (ORCPT ); Thu, 24 Feb 2022 04:26:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232087AbiBXJ0Z (ORCPT ); Thu, 24 Feb 2022 04:26:25 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A4D5279919; Thu, 24 Feb 2022 01:25:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645694756; x=1677230756; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=/gu7eQvzK90N7g7on/O4htPHyJktgVUTYPAZjxIQVF8=; b=fCElD1003i8OLwwe5De1ByyM+lwpOq4TmbIiwGx1Ovo/59KsEX4QCXn1 zsqAg77X0z4nHyNkbCOr3TvYbr/FQQoCOkmiG0K4RFCx8EZRvplUKzE4N dGVi5N2shJEDPCLQ98FaMpTjmylOs5Fm3GGw5HTPHfMs4g5TK2PWDMDpY 5Q43huP7BQFJVOmsLJvQqCxNPmF/p8NuCuQ4EnDXHCX1cXJUeHz+sLDod DW04Fzg0Mfcw4IDpLA/7GVFk0PjQJnTU+z8Cp4mi5diy3Nh4dM/6DqBX2 9u4H76wsaoMxNrFY4l77Sc6P/X2HEnR+X/FJiDrtbrU8FtaQSymbZNlef w==; X-IronPort-AV: E=McAfee;i="6200,9189,10267"; a="239586016" X-IronPort-AV: E=Sophos;i="5.88,393,1635231600"; d="scan'208";a="239586016" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 01:25:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,393,1635231600"; d="scan'208";a="639654731" Received: from unknown (HELO localhost.localdomain.sh.intel.com) ([10.238.175.107]) by orsmga004.jf.intel.com with ESMTP; 24 Feb 2022 01:25:50 -0800 From: Tianfei zhang To: hao.wu@intel.com, trix@redhat.com, mdf@kernel.org, yilun.xu@intel.com, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: corbet@lwn.net, Tianfei Zhang Subject: [PATCH v1] fpga: dfl: check feature type before parse irq info Date: Thu, 24 Feb 2022 04:22:42 -0500 Message-Id: <20220224092242.127081-1-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org From: Tianfei Zhang The feature ID of "Port User Interrupt" and the "PMCI Subsystem" are identical, 0x12, but one is for FME, other is for Port. It should check the feature type While parsing the irq info in parse_feature_irqs(). Fixes: 8d021039cbb5 ("fpga: dfl: parse interrupt info for feature devices on enumeration") Link: https://lore.kernel.org/linux-fpga/BN9PR11MB54833D7636348D62F931526CE33A9@BN9PR11MB5483.namprd11.prod.outlook.com/ Signed-off-by: Tianfei Zhang --- Documentation/fpga/dfl.rst | 5 +++++ drivers/fpga/dfl.c | 38 ++++++++++++++++++++++---------------- 2 files changed, 27 insertions(+), 16 deletions(-) diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index ef9eec71f6f3..9ce418da1876 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id. FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) could be a reference. +Individual DFL drivers are bound DFL devices based on Feature Type and Feature ID. +The definition of Feature Type and Feature ID can be found: + +https://github.com/OPAE/linux-dfl-feature-id/blob/master/dfl-feature-ids.rst + Location of DFLs on a PCI Device ================================ The original method for finding a DFL on a PCI device assumed the start of the diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index 599bb21d86af..6bff39ff21a0 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -940,9 +940,12 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, { void __iomem *base = binfo->ioaddr + ofst; unsigned int i, ibase, inr = 0; + enum dfl_id_type type; int virq; u64 v; + type = feature_dev_id_type(binfo->feature_dev); + /* * Ideally DFL framework should only read info from DFL header, but * current version DFL only provides mmio resources information for @@ -957,22 +960,25 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, * code will be added. But in order to be compatible to old version * DFL, the driver may still fall back to these quirks. */ - switch (fid) { - case PORT_FEATURE_ID_UINT: - v = readq(base + PORT_UINT_CAP); - ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); - inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); - break; - case PORT_FEATURE_ID_ERROR: - v = readq(base + PORT_ERROR_CAP); - ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); - break; - case FME_FEATURE_ID_GLOBAL_ERR: - v = readq(base + FME_ERROR_CAP); - ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); - break; + if (type == PORT_ID) { + switch (fid) { + case PORT_FEATURE_ID_UINT: + v = readq(base + PORT_UINT_CAP); + ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); + inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); + break; + case PORT_FEATURE_ID_ERROR: + v = readq(base + PORT_ERROR_CAP); + ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); + break; + } + } else if (type == FME_ID) { + if (fid == FME_FEATURE_ID_GLOBAL_ERR) { + v = readq(base + FME_ERROR_CAP); + ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); + } } if (!inr) {