| Message ID | 20220323085102.2297964-3-tianfei.zhang@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | check feature type for DFL irq parsing | expand |
On 23/03/22 15.51, Tianfei Zhang wrote: > +Individual DFL drivers are bound DFL devices based on Feature Type and Feature ID. > +The definition of Feature Type and Feature ID can be found: > + > +https://github.com/OPAE/linux-dfl-feature-id/blob/master/dfl-feature-ids.rst > + This doesn't answer "What is Feature Type and Feature ID?" question. I would like to see the answer and the feature list above in the kernel documentation. > +If you want to add a new feature ID for FPGA DFL feature device, you must submit a pull > +request to register a feature ID for DFL. Here is the DFL Feature ID Registry: > + > +https://github.com/OPAE/linux-dfl-feature-id > + Please explain, in this document, the PR procedure regarding feature ID registration.
> -----Original Message----- > From: Bagas Sanjaya <bagasdotme@gmail.com> > Sent: Wednesday, March 23, 2022 8:12 PM > To: Zhang, Tianfei <tianfei.zhang@intel.com>; Wu, Hao <hao.wu@intel.com>; > trix@redhat.com; mdf@kernel.org; Xu, Yilun <yilun.xu@intel.com>; linux- > fpga@vger.kernel.org; linux-doc@vger.kernel.org > Cc: corbet@lwn.net; rdunlap@infradead.org > Subject: Re: [PATCH v5 2/2] Documentation: fpga: dfl: add description of > Feature ID > > On 23/03/22 15.51, Tianfei Zhang wrote: > > +Individual DFL drivers are bound DFL devices based on Feature Type and > Feature ID. > > +The definition of Feature Type and Feature ID can be found: > > + > > +https://github.com/OPAE/linux-dfl-feature-id/blob/master/dfl-feature- > > +ids.rst > > + > > This doesn't answer "What is Feature Type and Feature ID?" question. > I would like to see the answer and the feature list above in the kernel > documentation. Feature Type is the device type of feature device, currently, we only support FME device and Port device now. Feature ID means the ID of feature device. Individual DFL drivers are bound DFL devices based on Feature Type and Feature ID after DFL enumeration. I think those detail information are in DFL specification, and it don't need put everything in kernel documentation. And I think the feature list maintains by an extra git repository will be better, and the users want to add a new feature ID must submit a pull request for this repo to register the new ID. > > > +If you want to add a new feature ID for FPGA DFL feature device, you > > +must submit a pull request to register a feature ID for DFL. Here is the DFL > Feature ID Registry: > > + > > +https://github.com/OPAE/linux-dfl-feature-id > > + > > Please explain, in this document, the PR procedure regarding feature ID > registration. In this documentation, it has a chapter talk about the PR, pls see the " Partial Reconfiguration" chapter. On DFL perspective, PR is a FME private feature device, the Feature Type is "0" (0 means FME), the feature ID is 0x5. FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) will be bound if it found a PR private feature device after DFL enumeration. > > -- > An old man doll... just what I always wanted! - Clara
diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index ef9eec71f6f3..231fe7a4d099 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -502,6 +502,16 @@ Developer only needs to provide a sub feature driver with matched feature id. FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) could be a reference. +Individual DFL drivers are bound DFL devices based on Feature Type and Feature ID. +The definition of Feature Type and Feature ID can be found: + +https://github.com/OPAE/linux-dfl-feature-id/blob/master/dfl-feature-ids.rst + +If you want to add a new feature ID for FPGA DFL feature device, you must submit a pull +request to register a feature ID for DFL. Here is the DFL Feature ID Registry: + +https://github.com/OPAE/linux-dfl-feature-id + Location of DFLs on a PCI Device ================================ The original method for finding a DFL on a PCI device assumed the start of the