| Message ID | 20220412061705.53721-3-tianfei.zhang@intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | check feature type for DFL irq parsing | expand |
On Tue, 12 Apr 2022, Tianfei Zhang wrote: > From: Tianfei zhang <tianfei.zhang@intel.com> > > This patch adds the description of feature id table in documentation. > > Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com> Hi Tianfei, Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > --- > v6: fix documentation from Hao's comment. > v5: fix documentation from Matthew's comment. > --- > Documentation/fpga/dfl.rst | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > index ef9eec71f6f3..15b670926084 100644 > --- a/Documentation/fpga/dfl.rst > +++ b/Documentation/fpga/dfl.rst > @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id. > FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) > could be a reference. > > +Please refer to below link to existing feature id table and guide for new feature > +ids application. > +https://github.com/OPAE/dfl-feature-id > + > + > Location of DFLs on a PCI Device > ================================ > The original method for finding a DFL on a PCI device assumed the start of the > -- > 2.26.2 > >
> On Tue, 12 Apr 2022, Tianfei Zhang wrote: > > > From: Tianfei zhang <tianfei.zhang@intel.com> > > > > This patch adds the description of feature id table in documentation. Please fix the title and commit message per your current modification as well. > > > > Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com> > > Hi Tianfei, > > Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > --- > > v6: fix documentation from Hao's comment. > > v5: fix documentation from Matthew's comment. > > --- > > Documentation/fpga/dfl.rst | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > > index ef9eec71f6f3..15b670926084 100644 > > --- a/Documentation/fpga/dfl.rst > > +++ b/Documentation/fpga/dfl.rst > > @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver > with matched feature id. > > FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) > > could be a reference. > > > > +Please refer to below link to existing feature id table and guide for new > feature > > +ids application. > > +https://github.com/OPAE/dfl-feature-id > > + > > + > > Location of DFLs on a PCI Device > > ================================ > > The original method for finding a DFL on a PCI device assumed the start of the > > -- > > 2.26.2 > > > >
> -----Original Message----- > From: Wu, Hao <hao.wu@intel.com> > Sent: Monday, April 18, 2022 9:08 AM > To: matthew.gerlach@linux.intel.com; Zhang, Tianfei > <tianfei.zhang@intel.com> > Cc: trix@redhat.com; mdf@kernel.org; Xu, Yilun <yilun.xu@intel.com>; linux- > fpga@vger.kernel.org; linux-doc@vger.kernel.org; rdunlap@infradead.org; > corbet@lwn.net > Subject: RE: [PATCH v6 2/2] Documentation: fpga: dfl: add description of feature > ids > > > On Tue, 12 Apr 2022, Tianfei Zhang wrote: > > > > > From: Tianfei zhang <tianfei.zhang@intel.com> > > > > > > This patch adds the description of feature id table in documentation. > > Please fix the title and commit message per your current modification as well. How about this tile and commit message: Title: Documentation: fpga: dfl: add link address of feature id table This patch adds the link address of feature id table in documentation. > > > > > > > Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com> > > > > Hi Tianfei, > > > > Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > > --- > > > v6: fix documentation from Hao's comment. > > > v5: fix documentation from Matthew's comment. > > > --- > > > Documentation/fpga/dfl.rst | 5 +++++ > > > 1 file changed, 5 insertions(+) > > > > > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > > > index ef9eec71f6f3..15b670926084 100644 > > > --- a/Documentation/fpga/dfl.rst > > > +++ b/Documentation/fpga/dfl.rst > > > @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature > > > driver > > with matched feature id. > > > FME Partial Reconfiguration Sub Feature driver (see > > > drivers/fpga/dfl-fme-pr.c) could be a reference. > > > > > > +Please refer to below link to existing feature id table and guide > > > +for new > > feature > > > +ids application. > > > +https://github.com/OPAE/dfl-feature-id > > > + > > > + > > > Location of DFLs on a PCI Device > > > ================================ > > > The original method for finding a DFL on a PCI device assumed the > > > start of the > > > -- > > > 2.26.2 > > > > > >
diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index ef9eec71f6f3..15b670926084 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -502,6 +502,11 @@ Developer only needs to provide a sub feature driver with matched feature id. FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) could be a reference. +Please refer to below link to existing feature id table and guide for new feature +ids application. +https://github.com/OPAE/dfl-feature-id + + Location of DFLs on a PCI Device ================================ The original method for finding a DFL on a PCI device assumed the start of the