Message ID | 20220421044744.3777983-5-nava.manne@xilinx.com (mailing list archive) |
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State | New |
Headers | show
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Wed, 20 Apr 2022 21:48:02 -0700 Envelope-to: git@xilinx.com, mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com, trix@redhat.com, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Received: from [10.140.6.60] (port=35750 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from <nava.manne@xilinx.com>) id 1nhOja-0002Sb-0W; Wed, 20 Apr 2022 21:48:02 -0700 From: Nava kishore Manne <nava.manne@xilinx.com> To: <mdf@kernel.org>, <hao.wu@intel.com>, <yilun.xu@intel.com>, <trix@redhat.com>, <michal.simek@xilinx.com>, <linux-fpga@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <git@xilinx.com> CC: Nava kishore Manne <nava.manne@xilinx.com> Subject: [PATCH v5 4/5] fpga: Use tab instead of space indentation Date: Thu, 21 Apr 2022 10:17:43 +0530 Message-ID: <20220421044744.3777983-5-nava.manne@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421044744.3777983-1-nava.manne@xilinx.com> References: <20220421044744.3777983-1-nava.manne@xilinx.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 483fd419-9da1-4ba2-5796-08da23522075 X-MS-TrafficTypeDiagnostic: DM6PR02MB7100:EE_ X-Microsoft-Antispam-PRVS: <DM6PR02MB7100566E871B9275CBC01E61C2F49@DM6PR02MB7100.namprd02.prod.outlook.com> X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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fpga: fix for coding style and kernel-doc issues
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diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 0bff783d1b61..5935b3d0abd5 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -18,9 +18,9 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o -obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o -obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o -obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o +obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o +obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o # FPGA Bridge Drivers obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o