From patchwork Thu Jun 9 15:47:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Bornyakov X-Patchwork-Id: 12875777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3DB3CCA473 for ; Thu, 9 Jun 2022 16:12:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244259AbiFIQK5 (ORCPT ); Thu, 9 Jun 2022 12:10:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236387AbiFIQKz (ORCPT ); Thu, 9 Jun 2022 12:10:55 -0400 Received: from mail.pr-group.ru (mail.pr-group.ru [178.18.215.3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98A333004D9; Thu, 9 Jun 2022 09:10:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=metrotek.ru; s=mail; h=from:subject:date:message-id:to:cc:mime-version:content-transfer-encoding: in-reply-to:references; bh=PYcsBoWzdiCutgNRzhzdQblCHgmrM9wgVrOHPOZNCxQ=; b=GhQFq1f+RXcF2suvxkFEbOxzZaQAxQJUo9lIlqjVeraslMiJv48iFCqMhN6bjGYhmBJ8QZjNEIjeP cpFq2wWJPhfpJJZxbNfgpk+TdIFPMPVuWd1qMxAFKO3wCkQP4gMeXDaekfEGwLhuHVnXALrEldy2MZ LwDhJhkGXxaq1tF1ACdzN4HypAVAJ3nNDciWGhzlw2+RjNt9lzpteHQYK6u60M84HIf2DQxJXQzHuV yGKuWSEyQONITdbd7cYnI2FzE9jTyOGN1op+AjOEgEHA6XutQx2/fqr0DfokQcdO9+jLZBdQUHZ3y9 WBuW+Cg/d2lPBz1fnvdXpb+KmN5o26Q== X-Kerio-Anti-Spam: Build: [Engines: 2.16.3.1424, Stamp: 3], Multi: [Enabled, t: (0.000009,0.008263)], BW: [Enabled, t: (0.000020,0.000001)], RTDA: [Enabled, t: (0.076305), Hit: No, Details: v2.40.0; Id: 15.52k9pa.1g54jmlnd.30e8; mclb], total: 0(700) X-Footer: bWV0cm90ZWsucnU= Received: from localhost.localdomain ([178.70.36.174]) (authenticated user i.bornyakov@metrotek.ru) by mail.pr-group.ru with ESMTPSA (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256 bits)); Thu, 9 Jun 2022 19:10:32 +0300 From: Ivan Bornyakov To: mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com, trix@redhat.com, corbet@lwn.net Cc: Ivan Bornyakov , Conor.Dooley@microchip.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, system@metrotek.ru, Ivan Bornyakov , Rob Herring Subject: [PATCH v17 4/4] dt-bindings: fpga: add binding doc for microchip-spi fpga mgr Date: Thu, 9 Jun 2022 18:47:52 +0300 Message-Id: <20220609154752.20781-5-i.bornyakov@metrotek.ru> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220609154752.20781-1-i.bornyakov@metrotek.ru> References: <20220609154752.20781-1-i.bornyakov@metrotek.ru> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Add Device Tree Binding doc for Microchip Polarfire FPGA Manager using slave SPI to load .dat formatted bitstream image. Signed-off-by: Ivan Bornyakov Reviewed-by: Rob Herring Acked-by: Xu Yilun --- .../fpga/microchip,mpf-spi-fpga-mgr.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml diff --git a/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml new file mode 100644 index 000000000000..aee45cb15592 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Polarfire FPGA manager. + +maintainers: + - Ivan Bornyakov + +description: + Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to + load the bitstream in .dat format. + +properties: + compatible: + enum: + - microchip,mpf-spi-fpga-mgr + + reg: + description: SPI chip select + maxItems: 1 + + spi-max-frequency: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + fpga_mgr@0 { + compatible = "microchip,mpf-spi-fpga-mgr"; + spi-max-frequency = <20000000>; + reg = <0>; + }; + };