From patchwork Tue Jun 21 15:38:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Bornyakov X-Patchwork-Id: 12889429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F9F5C43334 for ; Tue, 21 Jun 2022 15:41:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352993AbiFUPkN (ORCPT ); Tue, 21 Jun 2022 11:40:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352885AbiFUPkI (ORCPT ); Tue, 21 Jun 2022 11:40:08 -0400 Received: from mail.pr-group.ru (mail.pr-group.ru [178.18.215.3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DCC7027B32; Tue, 21 Jun 2022 08:40:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=metrotek.ru; s=mail; h=from:subject:date:message-id:to:cc:mime-version:content-transfer-encoding: in-reply-to:references; bh=XNWqwDT8OLiBMyF06PjFh1gIXEFKaOZYcVPPTh5+6oY=; b=dKdetUPtuywS7FQaEaBvXZgrkJsquUzuXfqW7wFpmJZ1l6WKG5HqgawMPLHl87ChPzimf0QG6qwfD xU60NblYCW1n4rNHiiM7cwpIgJfKk8kNHmb445rS0GXBAh8i3aZIck+FFs/zj0yzfu/XD9TL/G2xec +xoRNIdRmbKFhgD2ScypEU33Igfd09HNe8no+cKntF8je3+kO2TvsiQXBDP1tCvUvTrWBvBRuL5TfB V4BLEFWe5dZwqcIdnYNBDHBXbvlt+LyptKz8vxLpEyjQgCbQfo05vWANREHIZdzPjlaCmiBkiv7lWb RF/iaG3Nqu9qY+AVphuwN2/1+TLG00Q== X-Kerio-Anti-Spam: Build: [Engines: 2.16.3.1424, Stamp: 3], Multi: [Enabled, t: (0.000009,0.008053)], BW: [Enabled, t: (0.000019,0.000001)], RTDA: [Enabled, t: (0.070316), Hit: No, Details: v2.40.0; Id: 15.52k0bu.1g63emviq.1g9vs; mclb], total: 0(700) X-Footer: bWV0cm90ZWsucnU= Received: from h-e2.ddg ([85.143.252.66]) (authenticated user i.bornyakov@metrotek.ru) by mail.pr-group.ru with ESMTPSA (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256 bits)); Tue, 21 Jun 2022 18:39:46 +0300 From: Ivan Bornyakov To: mdf@kernel.org, hao.wu@intel.com, yilun.xu@intel.com, trix@redhat.com, corbet@lwn.net Cc: Ivan Bornyakov , conor.dooley@microchip.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, system@metrotek.ru, Rob Herring Subject: [PATCH v21 4/5] dt-bindings: fpga: add binding doc for microchip-spi fpga mgr Date: Tue, 21 Jun 2022 18:38:46 +0300 Message-Id: <20220621153847.103052-5-i.bornyakov@metrotek.ru> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220621153847.103052-1-i.bornyakov@metrotek.ru> References: <20220621153847.103052-1-i.bornyakov@metrotek.ru> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Add Device Tree Binding doc for Microchip Polarfire FPGA Manager using slave SPI to load .dat formatted bitstream image. Signed-off-by: Ivan Bornyakov Reviewed-by: Rob Herring Acked-by: Xu Yilun --- .../fpga/microchip,mpf-spi-fpga-mgr.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml diff --git a/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml new file mode 100644 index 000000000000..aee45cb15592 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/microchip,mpf-spi-fpga-mgr.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Polarfire FPGA manager. + +maintainers: + - Ivan Bornyakov + +description: + Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to + load the bitstream in .dat format. + +properties: + compatible: + enum: + - microchip,mpf-spi-fpga-mgr + + reg: + description: SPI chip select + maxItems: 1 + + spi-max-frequency: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + fpga_mgr@0 { + compatible = "microchip,mpf-spi-fpga-mgr"; + spi-max-frequency = <20000000>; + reg = <0>; + }; + };