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Wed, 24 Aug 2022 03:55:58 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT029.mail.protection.outlook.com (10.13.174.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5566.15 via Frontend Transport; Wed, 24 Aug 2022 03:55:57 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 23 Aug 2022 22:55:55 -0500 From: Nava kishore Manne To: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 2/4] bindings: fpga: Add binding doc for the zynqmp afi config driver Date: Wed, 24 Aug 2022 09:25:40 +0530 Message-ID: <20220824035542.706433-3-nava.kishore.manne@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220824035542.706433-1-nava.kishore.manne@amd.com> References: <20220824035542.706433-1-nava.kishore.manne@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 472d31fd-7036-47aa-e812-08da85848d5d X-MS-TrafficTypeDiagnostic: BN8PR12MB3251:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2022 03:55:57.8390 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 472d31fd-7036-47aa-e812-08da85848d5d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3251 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org Xilinx Zynq US+ MPSoC platform connect the PS to the programmable logic(PL) through the AXI port. This AXI port helps to establish the data path between the PS and PL. In-order to establish the proper communication data path between PS and PL the AXI port data path should be configured with the proper Bus-width values. This patch adds the binding document for the zynqmp afi config driver to handle the AXI port bus-width configurations and PS-PL resets. Signed-off-by: Nava kishore Manne --- .../bindings/fpga/xlnx,zynqmp-afi-fpga.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml new file mode 100644 index 000000000000..faae4951e991 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-afi-fpga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx ZynqMP AFI interface Manager. + +maintainers: + - Nava kishore Manne + +description: The Zynq UltraScale+ MPSoC Processing System core provides access + from PL masters to PS internal peripherals, and memory through AXI FIFO + interface(AFI) + +properties: + compatible: + items: + - enum: + - xlnx,zynqmp-afi-fpga + + resets: + description: + A list of phandles for resets listed in reset-names. + + reset-names: + items: + - const: pl0-rst + - const: pl1-rst + - const: pl2-rst + - const: pl3-rst + +patternProperties: + "^xlnx,afifm[0-6]-rd-bus-width$": + description: bus width used to configure the afifm-rd interface. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 32, 64, 128 ] + + "^xlnx,afifm[0-6]-wr-bus-width$": + description: bus width used to configure the afifm-wr interface. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 32, 64, 128 ] + + "^xlnx,afifs-ss[0-2]-bus-width$": + description: bus width used to configure the afifs interface. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 32, 64, 128 ] + +required: + - compatible + - xlnx,afifm0-rd-bus-width + - xlnx,afifm1-rd-bus-width + - xlnx,afifm2-rd-bus-width + - xlnx,afifm3-rd-bus-width + - xlnx,afifm4-rd-bus-width + - xlnx,afifm5-rd-bus-width + - xlnx,afifm6-rd-bus-width + - xlnx,afifm0-wr-bus-width + - xlnx,afifm1-wr-bus-width + - xlnx,afifm2-wr-bus-width + - xlnx,afifm3-wr-bus-width + - xlnx,afifm4-wr-bus-width + - xlnx,afifm5-wr-bus-width + - xlnx,afifm6-wr-bus-width + - xlnx,afifs-ss0-bus-width + - xlnx,afifs-ss1-bus-width + - xlnx,afifs-ss2-bus-width + +additionalProperties: false + +examples: + - | + #include + zynqmp-afi { + compatible = "xlnx,zynqmp-afi-fpga"; + xlnx,afifm0-rd-bus-width = <32>; + xlnx,afifm1-rd-bus-width = <32>; + xlnx,afifm2-rd-bus-width = <64>; + xlnx,afifm3-rd-bus-width = <128>; + xlnx,afifm4-rd-bus-width = <32>; + xlnx,afifm5-rd-bus-width = <64>; + xlnx,afifm6-rd-bus-width = <128>; + xlnx,afifm0-wr-bus-width = <32>; + xlnx,afifm1-wr-bus-width = <32>; + xlnx,afifm2-wr-bus-width = <64>; + xlnx,afifm3-wr-bus-width = <128>; + xlnx,afifm4-wr-bus-width = <32>; + xlnx,afifm5-wr-bus-width = <64>; + xlnx,afifm6-wr-bus-width = <128>; + xlnx,afifs-ss0-bus-width = <64>; + xlnx,afifs-ss1-bus-width = <64>; + xlnx,afifs-ss2-bus-width = <64>; + resets = <&zynqmp_reset ZYNQMP_RESET_PS_PL0>, + <&zynqmp_reset ZYNQMP_RESET_PS_PL1>, + <&zynqmp_reset ZYNQMP_RESET_PS_PL2>, + <&zynqmp_reset ZYNQMP_RESET_PS_PL3>; + reset-names = "pl0-rst", "pl1-rst", "pl2-rst", "pl3-rst"; + }; + +...