diff mbox series

[v2] uio: dfl: add IOPLL user-clock feature id

Message ID 20220826150116.16014-1-peter.colberg@intel.com (mailing list archive)
State Superseded
Headers show
Series [v2] uio: dfl: add IOPLL user-clock feature id | expand

Commit Message

Peter Colberg Aug. 26, 2022, 3:01 p.m. UTC
Add a Device Feature List (DFL) feature id [1] for the configurable
IOPLL user clock source, which can be used to configure the clock
speeds that are used for RTL logic that is programmed into the
Partial Reconfiguration (PR) region of an FPGA.

The IOPLL user-space driver [2] contains frequency tables [3]
with the specific user clock frequencies for an implementation.

For each desired frequency, the table values are produced by calling
the quartus tool, the same tool that generates the IOPLL RTL logic.
The quartus tool allows the RTL designer to select different options
which can affect the table values. The table-driven, user-space
driver allows for supporting future, modified implementations and
provides users the ability to modify the IOPLL implementation.

[1] https://github.com/OPAE/dfl-feature-id
[2] https://github.com/OPAE/opae-sdk/blob/a494f54a9f0356d0425edbff228f0254a4c70303/libraries/plugins/xfpga/usrclk/fpga_user_clk.c
[3] https://github.com/OPAE/opae-sdk/blob/a494f54a9f0356d0425edbff228f0254a4c70303/libraries/plugins/xfpga/usrclk/fpga_user_clk_freq.h

Signed-off-by: Peter Colberg <peter.colberg@intel.com>
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
---
 drivers/uio/uio_dfl.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Xu Yilun Aug. 27, 2022, 5:54 a.m. UTC | #1
On 2022-08-26 at 11:01:16 -0400, Peter Colberg wrote:
> Add a Device Feature List (DFL) feature id [1] for the configurable
> IOPLL user clock source, which can be used to configure the clock
> speeds that are used for RTL logic that is programmed into the
> Partial Reconfiguration (PR) region of an FPGA.
> 
> The IOPLL user-space driver [2] contains frequency tables [3]
> with the specific user clock frequencies for an implementation.
> 
> For each desired frequency, the table values are produced by calling
> the quartus tool, the same tool that generates the IOPLL RTL logic.
> The quartus tool allows the RTL designer to select different options
> which can affect the table values. The table-driven, user-space
> driver allows for supporting future, modified implementations and
> provides users the ability to modify the IOPLL implementation.
> 
> [1] https://github.com/OPAE/dfl-feature-id
> [2] https://github.com/OPAE/opae-sdk/blob/a494f54a9f0356d0425edbff228f0254a4c70303/libraries/plugins/xfpga/usrclk/fpga_user_clk.c
> [3] https://github.com/OPAE/opae-sdk/blob/a494f54a9f0356d0425edbff228f0254a4c70303/libraries/plugins/xfpga/usrclk/fpga_user_clk_freq.h
> 
> Signed-off-by: Peter Colberg <peter.colberg@intel.com>
> Signed-off-by: Russ Weight <russell.h.weight@intel.com>

Acked-by: Xu Yilun <yilun.xu@intel.com>

> ---
>  drivers/uio/uio_dfl.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/uio/uio_dfl.c b/drivers/uio/uio_dfl.c
> index 8f39cc8bb034..69e93f3e7faf 100644
> --- a/drivers/uio/uio_dfl.c
> +++ b/drivers/uio/uio_dfl.c
> @@ -46,10 +46,12 @@ static int uio_dfl_probe(struct dfl_device *ddev)
>  
>  #define FME_FEATURE_ID_ETH_GROUP	0x10
>  #define FME_FEATURE_ID_HSSI_SUBSYS	0x15
> +#define PORT_FEATURE_ID_IOPLL_USRCLK	0x14
>  
>  static const struct dfl_device_id uio_dfl_ids[] = {
>  	{ FME_ID, FME_FEATURE_ID_ETH_GROUP },
>  	{ FME_ID, FME_FEATURE_ID_HSSI_SUBSYS },
> +	{ PORT_ID, PORT_FEATURE_ID_IOPLL_USRCLK },
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(dfl, uio_dfl_ids);
> -- 
> 2.28.0
>
diff mbox series

Patch

diff --git a/drivers/uio/uio_dfl.c b/drivers/uio/uio_dfl.c
index 8f39cc8bb034..69e93f3e7faf 100644
--- a/drivers/uio/uio_dfl.c
+++ b/drivers/uio/uio_dfl.c
@@ -46,10 +46,12 @@  static int uio_dfl_probe(struct dfl_device *ddev)
 
 #define FME_FEATURE_ID_ETH_GROUP	0x10
 #define FME_FEATURE_ID_HSSI_SUBSYS	0x15
+#define PORT_FEATURE_ID_IOPLL_USRCLK	0x14
 
 static const struct dfl_device_id uio_dfl_ids[] = {
 	{ FME_ID, FME_FEATURE_ID_ETH_GROUP },
 	{ FME_ID, FME_FEATURE_ID_HSSI_SUBSYS },
+	{ PORT_ID, PORT_FEATURE_ID_IOPLL_USRCLK },
 	{ }
 };
 MODULE_DEVICE_TABLE(dfl, uio_dfl_ids);