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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF0001A0FB.mail.protection.outlook.com (10.167.242.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7025.12 via Frontend Transport; Wed, 22 Nov 2023 05:44:18 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Tue, 21 Nov 2023 23:44:17 -0600 From: Nava kishore Manne To: , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH 3/3] fpga: zynqmp: Add encrypted Bitstream loading support Date: Wed, 22 Nov 2023 11:14:04 +0530 Message-ID: <20231122054404.3764288-4-nava.kishore.manne@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231122054404.3764288-1-nava.kishore.manne@amd.com> References: <20231122054404.3764288-1-nava.kishore.manne@amd.com> Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FB:EE_|CH3PR12MB9343:EE_ X-MS-Office365-Filtering-Correlation-Id: 04674ec8-6cb5-45f9-1400-08dbeb1e11ae X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Nov 2023 05:44:18.0599 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04674ec8-6cb5-45f9-1400-08dbeb1e11ae X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9343 Adds support for both Device-key and user-key encrypted bitstream loading to the Xilinx ZynqMP Soc. Signed-off-by: Nava kishore Manne --- drivers/fpga/zynqmp-fpga.c | 53 ++++++++++++++++++++++++++-- include/linux/firmware/xlnx-zynqmp.h | 2 ++ 2 files changed, 52 insertions(+), 3 deletions(-) diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c index f3434e2c487b..8b0e4b8b5d99 100644 --- a/drivers/fpga/zynqmp-fpga.c +++ b/drivers/fpga/zynqmp-fpga.c @@ -15,16 +15,44 @@ /* Constant Definitions */ #define IXR_FPGA_DONE_MASK BIT(3) +#define ENCRYPTED_KEY_LEN 64 +#define AES_MATCH_STR_LEN 5 + /** * struct zynqmp_fpga_priv - Private data structure + * @aes_key: Pointer Aes key buffer * @dev: Device data structure * @flags: flags which is used to identify the bitfile type */ struct zynqmp_fpga_priv { + const char *aes_key; struct device *dev; u32 flags; }; +static int zynqmp_fpga_parse_aes_key(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t size) +{ + struct zynqmp_fpga_priv *priv = mgr->priv; + const char *str = "Key 0"; + + for (int i = 0; i < size; i++) { + if (!strncmp(str, &buf[i], AES_MATCH_STR_LEN)) { + buf += AES_MATCH_STR_LEN + 1; + while (buf[i] == ' ') + i++; + if (size - i < ENCRYPTED_KEY_LEN) + return -EINVAL; + priv->aes_key = &buf[i]; + + return 0; + } + } + + return -EINVAL; +} + static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr, struct fpga_image_info *info, const char *buf, size_t size) @@ -43,25 +71,43 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr, struct zynqmp_fpga_priv *priv; dma_addr_t dma_addr; u32 eemi_flags = 0; + size_t dma_size; char *kbuf; int ret; priv = mgr->priv; - kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); + if (priv->flags & FPGA_MGR_USRKEY_ENCRYPTED_BITSTREAM) + dma_size = size + ENCRYPTED_KEY_LEN; + else + dma_size = size; + + kbuf = dma_alloc_coherent(priv->dev, dma_size, &dma_addr, GFP_KERNEL); if (!kbuf) return -ENOMEM; memcpy(kbuf, buf, size); + if (priv->flags & FPGA_MGR_USRKEY_ENCRYPTED_BITSTREAM) { + eemi_flags |= XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_USERKEY; + memcpy(kbuf + size, priv->aes_key, ENCRYPTED_KEY_LEN); + } + wmb(); /* ensure all writes are done before initiate FW call */ if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG) eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL; - ret = zynqmp_pm_fpga_load(dma_addr, size, eemi_flags); + if (priv->flags & FPGA_MGR_ENCRYPTED_BITSTREAM) + eemi_flags |= XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_DEVKEY; + + if (priv->flags & FPGA_MGR_USRKEY_ENCRYPTED_BITSTREAM) + ret = zynqmp_pm_fpga_load(dma_addr, dma_addr + size, + eemi_flags); + else + ret = zynqmp_pm_fpga_load(dma_addr, size, eemi_flags); - dma_free_coherent(priv->dev, size, kbuf, dma_addr); + dma_free_coherent(priv->dev, dma_size, kbuf, dma_addr); return ret; } @@ -99,6 +145,7 @@ ATTRIBUTE_GROUPS(zynqmp_fpga); static const struct fpga_manager_ops zynqmp_fpga_ops = { .state = zynqmp_fpga_ops_state, + .parse_aes_key = zynqmp_fpga_parse_aes_key, .write_init = zynqmp_fpga_ops_write_init, .write = zynqmp_fpga_ops_write, }; diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index d1ea3898564c..e88f24870a77 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -83,6 +83,8 @@ */ #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) +#define XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_USERKEY BIT(3) +#define XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_DEVKEY BIT(4) /* FPGA Status Reg */ #define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U