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[2003:eb:5f2e:9b00:e0c2:68ab:7636:554b]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a72af0c9d06sm69644166b.18.2024.06.28.08.24.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Jun 2024 08:24:16 -0700 (PDT) From: iansdannapel@gmail.com To: Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Neil Armstrong , Sebastian Reichel , Chris Morgan , Michael Riesch , =?utf-8?b?UmFmYcWCIE1pxYJl?= =?utf-8?b?Y2tp?= , Andre Przywara , Linus Walleij , linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ian Dannapel Subject: [PATCH v2 2/3] dt-bindings: fpga: Add Efinix serial SPI programming bindings Date: Fri, 28 Jun 2024 17:23:47 +0200 Message-Id: <20240628152348.61133-3-iansdannapel@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240628152348.61133-1-iansdannapel@gmail.com> References: <20240620144217.124733-1-iansdannapel@gmail.com> <20240628152348.61133-1-iansdannapel@gmail.com> Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ian Dannapel Add device tree binding documentation for configuring Efinix FPGA using serial SPI passive programming mode. Signed-off-by: Ian Dannapel Reviewed-by: Conor Dooley --- .../fpga/efinix,trion-spi-passive.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml new file mode 100644 index 000000000000..d44a9d0627b6 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/efinix,trion-spi-passive.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Efinix SPI FPGA Manager + +maintainers: + - Ian Dannapel + +description: | + Efinix Trion and Titanium Series FPGAs support a method of loading the + bitstream over what is referred to as "SPI Passive Programming". + Only serial (1x bus width) is supported, setting the programming mode + is not in the scope the this manager and must be done elsewhere. + + References: + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - efinix,trion-spi-passive + - efinix,titanium-spi-passive + + spi-cpha: true + + spi-cpol: true + + spi-max-frequency: + maximum: 25000000 + + reg: + maxItems: 1 + + creset-gpios: + description: + reset and re-configuration trigger pin (low active) + maxItems: 1 + + cs-gpios: + description: + chip-select pin (low active) + maxItems: 1 + + cdone-gpios: + description: + optional configuration done status pin (high active) + maxItems: 1 + +required: + - compatible + - reg + - creset-gpios + - cs-gpios + +additionalProperties: false + +examples: + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + fpga_mgr_spi: fpga-mgr@0 { + compatible = "efinix,trion-spi-passive"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-cpha; + spi-cpol; + creset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; +...