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[2003:eb:5f03:0:4dce:df23:62c2:6f55]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abf1a60de5esm209289566b.100.2025.02.28.01.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 01:47:46 -0800 (PST) From: iansdannapel@gmail.com To: linux-fpga@vger.kernel.org Cc: Moritz Fischer , Wu Hao , Xu Yilun , Tom Rix , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jonathan Cameron , =?utf-8?b?UmFmYcWCIE1pxYJl?= =?utf-8?b?Y2tp?= , Aradhya Bhatia , Ian Dannapel , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [v4 3/3] fpga-mgr: Add Efinix SPI programming driver Date: Fri, 28 Feb 2025 10:47:32 +0100 Message-ID: <20250228094732.54642-4-iansdannapel@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250228094732.54642-1-iansdannapel@gmail.com> References: <20250228094732.54642-1-iansdannapel@gmail.com> Precedence: bulk X-Mailing-List: linux-fpga@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ian Dannapel Add a new driver for loading binary firmware to configuration RAM using "SPI passive mode" on Efinix FPGAs. Signed-off-by: Ian Dannapel --- drivers/fpga/Kconfig | 7 ++ drivers/fpga/Makefile | 1 + drivers/fpga/efinix-spi.c | 212 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 220 insertions(+) create mode 100644 drivers/fpga/efinix-spi.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 37b35f58f0df..b5d60ba62900 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -83,6 +83,13 @@ config FPGA_MGR_XILINX_SPI FPGA manager driver support for Xilinx FPGA configuration over slave serial interface. +config FPGA_MGR_EFINIX_SPI + tristate "Efinix FPGA configuration over SPI" + depends on SPI + help + FPGA manager driver support for Efinix FPGAs configuration over SPI + (passive mode only). + config FPGA_MGR_ICE40_SPI tristate "Lattice iCE40 SPI" depends on OF && SPI diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index aeb89bb13517..adbd51d2cd1e 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o obj-$(CONFIG_FPGA_MGR_XILINX_CORE) += xilinx-core.o obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP) += xilinx-selectmap.o obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o +obj-$(CONFIG_FPGA_MGR_EFINIX_SPI) += efinix-spi.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o diff --git a/drivers/fpga/efinix-spi.c b/drivers/fpga/efinix-spi.c new file mode 100644 index 000000000000..07885110a8a8 --- /dev/null +++ b/drivers/fpga/efinix-spi.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * FPGA Manager Driver for Efinix + * + * Copyright (C) 2025 iris-GmbH infrared & intelligent sensors + * + * Ian Dannapel + * + * Load Efinix FPGA firmware over SPI using the serial configuration interface. + * + * Note 1: Only passive mode (host initiates transfer) is currently supported. + * Note 2: Topaz and Titanium support is based on documentation but remains + * untested. + */ + +#include +#include +#include +#include +#include +#include + +struct efinix_spi_conf { + struct spi_device *spi; + struct gpio_desc *cdone; + struct gpio_desc *reset; +}; + +static void efinix_spi_reset(struct efinix_spi_conf *conf) +{ + gpiod_set_value(conf->reset, 1); + /* tCRESET_N > 320 ns */ + usleep_range(1, 2); + gpiod_set_value(conf->reset, 0); + + /* tDMIN > 32 us */ + usleep_range(35, 40); +} + +static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr) +{ + struct efinix_spi_conf *conf = mgr->priv; + + if (conf->cdone && gpiod_get_value(conf->cdone) == 1) + return FPGA_MGR_STATE_OPERATING; + + return FPGA_MGR_STATE_UNKNOWN; +} + +static int efinix_spi_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { + dev_err(&mgr->dev, "Partial reconfiguration not supported\n"); + return -EOPNOTSUPP; + } + return 0; +} + +static int efinix_spi_write(struct fpga_manager *mgr, const char *buf, + size_t count) +{ + struct efinix_spi_conf *conf = mgr->priv; + int ret; + struct spi_message message; + struct spi_transfer assert_cs = { + .cs_change = 1 + }; + struct spi_transfer write_xfer = { + .tx_buf = buf, + .len = count + }; + struct spi_transfer clk_cycles = { + .len = 13, // > 100 clock cycles + .tx_buf = NULL + }; + u8 *dummy_buf; + + dummy_buf = kzalloc(13, GFP_KERNEL); + if (!dummy_buf) { + ret = -ENOMEM; + goto fail; + } + + spi_bus_lock(conf->spi->controller); + spi_message_init(&message); + spi_message_add_tail(&assert_cs, &message); + ret = spi_sync_locked(conf->spi, &message); + if (ret) + goto fail_unlock; + + /* reset with asserted cs */ + efinix_spi_reset(conf); + + spi_message_init(&message); + spi_message_add_tail(&write_xfer, &message); + + clk_cycles.tx_buf = dummy_buf; + spi_message_add_tail(&clk_cycles, &message); + + ret = spi_sync_locked(conf->spi, &message); + if (ret) + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", ret); + +fail_unlock: + spi_bus_unlock(conf->spi->controller); + kfree(dummy_buf); +fail: + return ret; +} + +static int efinix_spi_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + struct efinix_spi_conf *conf = mgr->priv; + unsigned long timeout = + jiffies + usecs_to_jiffies(info->config_complete_timeout_us); + bool expired = false; + int done; + + if (conf->cdone) { + while (!expired) { + expired = time_after(jiffies, timeout); + + done = gpiod_get_value(conf->cdone); + if (done < 0) + return done; + + if (done) + break; + } + } + + if (expired) + return -ETIMEDOUT; + + /* tUSER > 25 us */ + usleep_range(30, 35); + return 0; +} + +static const struct fpga_manager_ops efinix_spi_ops = { + .state = efinix_spi_state, + .write_init = efinix_spi_write_init, + .write = efinix_spi_write, + .write_complete = efinix_spi_write_complete, +}; + +static int efinix_spi_probe(struct spi_device *spi) +{ + struct efinix_spi_conf *conf; + struct fpga_manager *mgr; + + conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL); + if (!conf) + return -ENOMEM; + + conf->spi = spi; + + conf->reset = devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(conf->reset)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->reset), + "Failed to get RESET gpio\n"); + + if (!(spi->mode & SPI_CPHA) || !(spi->mode & SPI_CPOL)) + return dev_err_probe(&spi->dev, -EINVAL, + "Unsupported SPI mode, set CPHA and CPOL\n"); + + conf->cdone = devm_gpiod_get_optional(&spi->dev, "cdone", GPIOD_IN); + if (IS_ERR(conf->cdone)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->cdone), + "Failed to get CDONE gpio\n"); + + mgr = devm_fpga_mgr_register(&spi->dev, + "Efinix FPGA Manager", + &efinix_spi_ops, conf); + + return PTR_ERR_OR_ZERO(mgr); +} + +static const struct of_device_id efinix_spi_of_match[] = { + { .compatible = "efinix,trion-spi", }, + { .compatible = "efinix,titanium-spi", }, + { .compatible = "efinix,topaz-spi", }, + { .compatible = "efinix,fpga-spi", }, + {} +}; +MODULE_DEVICE_TABLE(of, efinix_spi_of_match); + +static const struct spi_device_id efinix_ids[] = { + { "trion-spi", 0 }, + { "titanium-spi", 0 }, + { "topaz-spi", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(spi, efinix_ids); + +static struct spi_driver efinix_spi_driver = { + .driver = { + .name = "efinix-spi", + .of_match_table = efinix_spi_of_match, + }, + .probe = efinix_spi_probe, + .id_table = efinix_ids, +}; + +module_spi_driver(efinix_spi_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Ian Dannapel "); +MODULE_DESCRIPTION("Efinix FPGA SPI Programming Driver (Topaz/Titanium untested)");