From patchwork Wed Mar 6 07:30:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Odelu Kukatla X-Patchwork-Id: 13583426 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A65625D46D; Wed, 6 Mar 2024 07:30:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709710261; cv=none; b=BwcS6T+ktbZ8rX6u/HD1GotN7sXa4Whn3YaBlD58agQ2HiaY+2VQqdF5rZvvGLpqSBpDkfm6Dzj7yYgB3tM+8Az2kVwOK3Hynnh4TVVeX7WNPrlgK1G28FRZFMbi1kff5XX/DJy4GyHCzm+iVL+RgPiONWGvzWumX/OZ38LCI98= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709710261; c=relaxed/simple; bh=J8rAfTB8Dz0cD0ouGjdO5KN4NNn2oSqBrYvKTdOIgjc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bVSFIbdlZ5h7cZPBg6U/NHAmh/LoA//3/wiVHSVD3i4L5nZ7cblm6/kZDp081uTeMSoARZpytflEE2gRyCNtU5Bg9TE7DLDBceze8nQ/KwB+m9ZGOKCVIjQTuPSxFwplFFkoAeQlBI3JN8unCMx0IhTsP6Iov2d4pv/qfO6WAMU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=euJqDinB; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="euJqDinB" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4264GgYL027191; Wed, 6 Mar 2024 07:30:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=oZo2YnbccVAuXSnZc+lW Ut35fh0qCOdd/MVID34SqTg=; b=euJqDinB1JwTSflqIulR06dODlb5z/QDkVWy xAjqjdDylXfYEIQAEKqqpcGPX3indIM+q/3tp+4U8ZMGtSCc+iT9txDc8+WLpiAG WegMizqNFjuju98xOlS8viGYovSkOWh+qde1917jo395X7xVU38bftnx1+mrwNNH tvwnJJxruYfAwyc3Zy1volk9HfIQGFx44arePbgyeFnouCVPWjOyl7wCG7CD9rsg MctzqubUTbRfOuI5GJbb/8lXG/tXD6SKhOInIo7lN1fA2Fbt7Vp++ikYrsc2Ks/4 MqedFhiCeq7ueerpz2fHNjx4vfgSyjisostiALyHn6AmmQEknA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3wp2bptc86-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 06 Mar 2024 07:30:55 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4267Utn3018903 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 6 Mar 2024 07:30:55 GMT Received: from hu-okukatla-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 5 Mar 2024 23:30:50 -0800 From: Odelu Kukatla To: Bjorn Andersson , Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Kees Cook , , "Gustavo A . R . Silva" , , , , , , , Subject: [PATCH v3 3/4] dt-bindings: interconnect: add clock property to enable QOS on SC7280 Date: Wed, 6 Mar 2024 13:00:15 +0530 Message-ID: <20240306073016.2163-4-quic_okukatla@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240306073016.2163-1-quic_okukatla@quicinc.com> References: <20240306073016.2163-1-quic_okukatla@quicinc.com> Precedence: bulk X-Mailing-List: linux-hardening@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: aBmVuAPHHo95AXST6M397EKHA1YvD0Bq X-Proofpoint-ORIG-GUID: aBmVuAPHHo95AXST6M397EKHA1YvD0Bq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-06_04,2024-03-05_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 mlxscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 clxscore=1015 malwarescore=0 spamscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2403060058 Added clock property to enable clocks required for accessing qos registers. Signed-off-by: Odelu Kukatla --- .../interconnect/qcom,sc7280-rpmh.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml index b135597d9489..758a6e924037 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml @@ -53,10 +53,50 @@ allOf: required: - reg + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-aggre1-noc + - qcom,sc7280-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false + unevaluatedProperties: false examples: - | + #include interconnect { compatible = "qcom,sc7280-clk-virt"; #interconnect-cells = <2>; @@ -69,3 +109,12 @@ examples: #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; + + interconnect@16e0000 { + reg = <0x016e0000 0x1c080>; + compatible = "qcom,sc7280-aggre1-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + };