From patchwork Mon May 20 15:49:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie Delaunay X-Patchwork-Id: 13668437 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D577E136E37; Mon, 20 May 2024 15:52:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716220328; cv=none; b=TsYBEDkA7p+Vl593o3ZlQGGGb4Qt+kATII3qhaNy5RZxPR7oi+00MdypcVQ71odzh7m0fDxv0a0Zzdq1B1QnVHQa/8zoNDOIgBQby9dVox7f4g52yMkavL3g0rClcyd41K86y+O9W7Faxg+9w3oAbN4akAywE3TkDQLCYbNMCiw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716220328; c=relaxed/simple; bh=N5/K7mj9lsm2JWZFGneYfqbcFzXhqrIIZeD8wxiKWpE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=k1Lj9lX2rC+rtt99H8zd+0cVKGu/nOYxP9Iprrvdnn+5VoUt2YuWFkHmSUpiPMYNEcXNya/zrkGfEqiaoUojPRbbW1tRJI0Vagz84LEkk6vYqOVmF4fDDGG/tqqloax6ptuJ7w0qykxuJT11vxHSFNjpm67xW8D5BKuzRXSmrro= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=0WGD+3cF; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="0WGD+3cF" Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 44KDxJsG030261; Mon, 20 May 2024 17:51:47 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=hsel/3AnsWqMvcvLhKt+H3+n/klED6301J96xkMZlkc=; b=0W GD+3cF8z4IyOBXZauTkTquEUNFKQH/4Yab55hkcXBAbfwldAcw11xcwfbSR8IekH g4MuRTN1JZVyKLULeYCqufddHyb9eed8lOzpW6fF9meg9M1paRkLNVYwACaIs3bT BvMw0oBmwn7ymEjlxRpc0CLPgHhgEE4E+pE+axacT/HnxzbV2dRIZIL32vwHLDLL hUUIAwX8t021d2xfLuI67JAA6uGWDkjh9KjXfuxf/apguTgvtbpUmARsJ0ZkbR9U lDX8rUeWykA0iLUdUeOb6+a5lRm3RD/T3QKoKtoJU9ElHnf/WubP8fRQiySXGuDn lPlG6yPrs8HwZiQILMvA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3y779hnn2n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 20 May 2024 17:51:47 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id D240F40044; Mon, 20 May 2024 17:51:42 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 0C1F7226FBD; Mon, 20 May 2024 17:50:59 +0200 (CEST) Received: from localhost (10.252.8.132) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 20 May 2024 17:50:58 +0200 From: Amelie Delaunay To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , , Amelie Delaunay Subject: [PATCH v3 08/12] dmaengine: stm32-dma3: add device_pause and device_resume ops Date: Mon, 20 May 2024 17:49:44 +0200 Message-ID: <20240520154948.690697-9-amelie.delaunay@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240520154948.690697-1-amelie.delaunay@foss.st.com> References: <20240520154948.690697-1-amelie.delaunay@foss.st.com> Precedence: bulk X-Mailing-List: linux-hardening@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-20_05,2024-05-17_03,2024-05-17_01 STM32 DMA3 controller is able to suspend an ongoing transfer (the transfer is suspended after the ongoing burst is flushed to the destination) and resume it from the point it was suspended. No need to reconfigure any register. Signed-off-by: Amelie Delaunay --- drivers/dma/stm32/stm32-dma3.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/dma/stm32/stm32-dma3.c b/drivers/dma/stm32/stm32-dma3.c index d379857d7aef..30cb18f382dc 100644 --- a/drivers/dma/stm32/stm32-dma3.c +++ b/drivers/dma/stm32/stm32-dma3.c @@ -1249,6 +1249,35 @@ static int stm32_dma3_config(struct dma_chan *c, struct dma_slave_config *config return 0; } +static int stm32_dma3_pause(struct dma_chan *c) +{ + struct stm32_dma3_chan *chan = to_stm32_dma3_chan(c); + int ret; + + ret = stm32_dma3_chan_suspend(chan, true); + if (ret) + return ret; + + chan->dma_status = DMA_PAUSED; + + dev_dbg(chan2dev(chan), "vchan %pK: paused\n", &chan->vchan); + + return 0; +} + +static int stm32_dma3_resume(struct dma_chan *c) +{ + struct stm32_dma3_chan *chan = to_stm32_dma3_chan(c); + + stm32_dma3_chan_suspend(chan, false); + + chan->dma_status = DMA_IN_PROGRESS; + + dev_dbg(chan2dev(chan), "vchan %pK: resumed\n", &chan->vchan); + + return 0; +} + static int stm32_dma3_terminate_all(struct dma_chan *c) { struct stm32_dma3_chan *chan = to_stm32_dma3_chan(c); @@ -1485,6 +1514,8 @@ static int stm32_dma3_probe(struct platform_device *pdev) dma_dev->device_prep_dma_cyclic = stm32_dma3_prep_dma_cyclic; dma_dev->device_caps = stm32_dma3_caps; dma_dev->device_config = stm32_dma3_config; + dma_dev->device_pause = stm32_dma3_pause; + dma_dev->device_resume = stm32_dma3_resume; dma_dev->device_terminate_all = stm32_dma3_terminate_all; dma_dev->device_synchronize = stm32_dma3_synchronize; dma_dev->device_tx_status = dma_cookie_status;