From patchwork Wed Dec 11 03:42:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 13902907 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50200241F3A; Wed, 11 Dec 2024 03:43:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733888589; cv=none; b=aIk1FUdgT/j+thLnjfxKCuF2lMeGaxPTvbF6lDh2g7z9HRAeXKrvYFRXbbDKalINtI3YpozDeQ+ozP7QHhjU0m7MHI5CKp4bH7XcNwf/KL3u01rFM3gwdC85AJmdKLGDPOHt6zgk3T3gGPpnVx/OMvJ01vhFch2U4fw9COYX8p0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733888589; c=relaxed/simple; bh=XLzhI18UDFof7TnKQ2OLeiagwCRrbKbtW4Xo582f/jI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cWrqfcd3B/tsQFpG0C19TmiuKUGUmWrtR47+1GoRsZ/xogF23b/hz4fbEub4TznH2OnRErDeiiYfwTT/6Z8xvjKhB2Pjll+CUT4CXrBFbGua0obdq5+i64URcy5BUNc/Luti+vm0D1qhxJ8zT9NfB+aZU/Q07j7iGaTdHE83HMs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TIk60EnX; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TIk60EnX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733888587; x=1765424587; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=XLzhI18UDFof7TnKQ2OLeiagwCRrbKbtW4Xo582f/jI=; b=TIk60EnXnfzp0KI75y7eZmZJ/7LkwPPF6RrVz5n+91IkRZ79ls43/wHG GCkCyhCU9Vdq+6kyvFBZf+Es/kZzyYcubX30MP7HmDBFAubNDg5ddvNid q/hkZJifjnFLz/iHZpe9igj4DYdckc+Qofv0Pp/jZ27ZQ03+eiyQ4fByl nrtqsxCasGoi7H3fHKzu3IJmR6yC4noQE4NtqGKO1nEkOG/n9TBaKtXTo b+D6StvaYvppnIVqIL8YzRHg2kfDRkjGmwjpglzJmzltGRIcD0HoKNy3w iItRQAigIK79nAKvweKlcMMEGEz3gaCvyOz2Keg+5EVaBwfTMe9cM5hy8 A==; X-CSE-ConnectionGUID: EB1qmJ+ET6adPFZjlNkjIg== X-CSE-MsgGUID: ElefW8SjQxi65XNIMPnCRw== X-IronPort-AV: E=McAfee;i="6700,10204,11282"; a="34178180" X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="34178180" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2024 19:43:07 -0800 X-CSE-ConnectionGUID: S+PVhy/+R4Wyhd5xu0dKsg== X-CSE-MsgGUID: NWKdIKrCTIKecF1QIIj30Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="95504280" Received: from lstrano-mobl6.amr.corp.intel.com (HELO localhost) ([10.125.109.231]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2024 19:43:06 -0800 From: Ira Weiny Date: Tue, 10 Dec 2024 21:42:34 -0600 Subject: [PATCH v8 19/21] cxl/mem: Trace Dynamic capacity Event Record Precedence: bulk X-Mailing-List: linux-hardening@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241210-dcd-type2-upstream-v8-19-812852504400@intel.com> References: <20241210-dcd-type2-upstream-v8-0-812852504400@intel.com> In-Reply-To: <20241210-dcd-type2-upstream-v8-0-812852504400@intel.com> To: Dave Jiang , Fan Ni , Jonathan Cameron , Jonathan Corbet , Andrew Morton , Kees Cook , "Gustavo A. R. Silva" Cc: Dan Williams , Davidlohr Bueso , Alison Schofield , Vishal Verma , Ira Weiny , linux-cxl@vger.kernel.org, linux-doc@vger.kernel.org, nvdimm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org X-Mailer: b4 0.15-dev-2a633 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733888537; l=3533; i=ira.weiny@intel.com; s=20221211; h=from:subject:message-id; bh=XLzhI18UDFof7TnKQ2OLeiagwCRrbKbtW4Xo582f/jI=; b=lxCviQhZ+K9W6AWm5ginOT5v7O+l9Zzo56ePraNfX4RurYfjfU+tDqjTIdxxc1eGPO5aSzbtL z1sCu8WZWoxDrm/4c7BIS4rVAFfnCvWF5PB/rSNevWb91D1p/O0ZkFJ X-Developer-Key: i=ira.weiny@intel.com; a=ed25519; pk=noldbkG+Wp1qXRrrkfY1QJpDf7QsOEthbOT7vm0PqsE= CXL rev 3.1 section 8.2.9.2.1 adds the Dynamic Capacity Event Records. User space can use trace events for debugging of DC capacity changes. Add DC trace points to the trace log. Based on an original patch by Navneet Singh. Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Fan Ni Signed-off-by: Ira Weiny --- drivers/cxl/core/mbox.c | 4 +++ drivers/cxl/core/trace.h | 65 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index e6789b59be1b361c1cfcb8d0e5b1ef64cd6555fd..133ef4dbe2a320e17d425ee280750b9757357f68 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -991,6 +991,10 @@ static void __cxl_event_trace_record(const struct cxl_memdev *cxlmd, ev_type = CXL_CPER_EVENT_DRAM; else if (uuid_equal(uuid, &CXL_EVENT_MEM_MODULE_UUID)) ev_type = CXL_CPER_EVENT_MEM_MODULE; + else if (uuid_equal(uuid, &CXL_EVENT_DC_EVENT_UUID)) { + trace_cxl_dynamic_capacity(cxlmd, type, &record->event.dcd); + return; + } cxl_event_trace_record(cxlmd, type, ev_type, uuid, &record->event); } diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index 8389a94adb1a681827209db46360d3d57c6672ce..ea819ea04a41a42636c1f612682a796a40ef5950 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -742,6 +742,71 @@ TRACE_EVENT(cxl_poison, ) ); +/* + * Dynamic Capacity Event Record - DER + * + * CXL rev 3.1 section 8.2.9.2.1.6 Table 8-50 + */ + +#define CXL_DC_ADD_CAPACITY 0x00 +#define CXL_DC_REL_CAPACITY 0x01 +#define CXL_DC_FORCED_REL_CAPACITY 0x02 +#define CXL_DC_REG_CONF_UPDATED 0x03 +#define show_dc_evt_type(type) __print_symbolic(type, \ + { CXL_DC_ADD_CAPACITY, "Add capacity"}, \ + { CXL_DC_REL_CAPACITY, "Release capacity"}, \ + { CXL_DC_FORCED_REL_CAPACITY, "Forced capacity release"}, \ + { CXL_DC_REG_CONF_UPDATED, "Region Configuration Updated" } \ +) + +TRACE_EVENT(cxl_dynamic_capacity, + + TP_PROTO(const struct cxl_memdev *cxlmd, enum cxl_event_log_type log, + struct cxl_event_dcd *rec), + + TP_ARGS(cxlmd, log, rec), + + TP_STRUCT__entry( + CXL_EVT_TP_entry + + /* Dynamic capacity Event */ + __field(u8, event_type) + __field(u16, hostid) + __field(u8, region_id) + __field(u64, dpa_start) + __field(u64, length) + __array(u8, tag, CXL_EXTENT_TAG_LEN) + __field(u16, sh_extent_seq) + ), + + TP_fast_assign( + CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); + + /* Dynamic_capacity Event */ + __entry->event_type = rec->event_type; + + /* DCD event record data */ + __entry->hostid = le16_to_cpu(rec->host_id); + __entry->region_id = rec->region_index; + __entry->dpa_start = le64_to_cpu(rec->extent.start_dpa); + __entry->length = le64_to_cpu(rec->extent.length); + memcpy(__entry->tag, &rec->extent.tag, CXL_EXTENT_TAG_LEN); + __entry->sh_extent_seq = le16_to_cpu(rec->extent.shared_extn_seq); + ), + + CXL_EVT_TP_printk("event_type='%s' host_id='%d' region_id='%d' " \ + "starting_dpa=%llx length=%llx tag=%pU " \ + "shared_extent_sequence=%d", + show_dc_evt_type(__entry->event_type), + __entry->hostid, + __entry->region_id, + __entry->dpa_start, + __entry->length, + __entry->tag, + __entry->sh_extent_seq + ) +); + #endif /* _CXL_EVENTS_H */ #define TRACE_INCLUDE_FILE trace