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BY1PR0301MB1285; 5:wjFewv4GqhWwPX2aAs+3p3h3/ZgNr9s8LXtvKGVChQMgGc5On8tAMa6i4elQAEzCK9zX8IILSdz09YUSGbHeD0u/nlDYN0CSysQyMMd790e1uf/tCH2n4L55MNmOAoptBBLAZZoFU4YknHz1nGeUkQ==; 24:JkI0Xo7HlgV3f2cF8NTMn6Vb1RCg8LRJmtR0+9QXOehpUK3YpEDs4Tx99S0V0iaL5ooVO9RE4CDx0F25f6Tyb5wTrxcQcnPtQRNL28WhchU=; 20:O+CmUpze9aAR3tPNIpUqpRdESzkT1nNt6G0AQ6uDeog88MHYa7zrbko5xBQaxr2AItP6epaMvicgUvHWlVMji3OLRI1b6s+/l1LAfaSOWRu2ewpKIG1w7IvfKj8VYWjpJqY0oH4ceNf4bjrFH3Dr7iRh75IjDRK9KDdgjOgpqsI= X-OriginatorOrg: opensource.altera.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Mar 2016 19:08:59.4687 (UTC) X-MS-Exchange-CrossTenant-Id: fbd72e03-d4a5-4110-adce-614d51f2077a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fbd72e03-d4a5-4110-adce-614d51f2077a; Ip=[66.35.236.227]; Helo=[sj-itexedge03.altera.priv.altera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0301MB1285 Sender: linux-hwmon-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thor Thayer The Altera Arria10 Devkit System Resource chip is a Multi-Function Device, it has two subdevices: - GPIO - HWMON This patch adds documentation for the Altera A10-SR DT bindings. Signed-off-by: Thor Thayer --- .../devicetree/bindings/mfd/altera-a10sr.txt | 35 ++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/altera-a10sr.txt diff --git a/Documentation/devicetree/bindings/mfd/altera-a10sr.txt b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt new file mode 100644 index 0000000..564c761 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/altera-a10sr.txt @@ -0,0 +1,35 @@ +* Altera Arria10 Development Kit System Resource Chip + +Required parent device properties: +- compatible : "altr,altr_a10sr" +- spi-max-frequency : Maximum SPI frequency. +- reg : the SPI Chip Select address for the Arria10 System Resource chip + +The A10SR consists of this varied group of sub-devices: + +Device Description +------ ---------- +altr_a10sr_gpio GPIO Controller +altr_a10sr_hwmon Hardware Monitor + +The LEDs are implemented entirely in the device tree using +the gpio-led framework. + +Example: + + a10-sr: a10-sr@0 { + compatible = "altr,altr-a10sr"; + reg = <0>; + spi-max-frequency = <100000>; + + a10sr_gpio: a10sr_gpio { + compatible = "altr,a10sr-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + }; + + a10sr_hwmon: a10sr_hwmon { + compatible = "altr,a10sr-hwmon"; + }; + };