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BY1PR0301MB1286; 5:sJ/mQi0D25/OYGPcQNrqysnkFdMol45MlVgLJXZDrjdRIimus1oXGdnJ4qsyGUtww4hLs94LxOcteG4poPifICWjCDiNJjRadtoMGaWW4/x/m+W7eLNsCBdGlnAryfiHltd8JP+o9jxeBo9SebdtqA==; 24:f8F6KzL7V6OM7mwtoAgKgNAwrrIkt/46VJZzUNeMIagqNW/eUNjftqWQgbGkjCmTL9DLiq7o2TT9pituC4cAuYHL8wjeIFJOpDEHvMoaLwM=; 20:YUPBMV0pP4vayV1MTpy9qW0+ONv9NrKfnvcdAvDQae0NgjKAtQmfbbrSHJ4qXfdtbGqHfMz8b5Ts90fXwc9sM4/8BdLURoLlFtc4cNkYXVwQSC2mNBgu5NQJRkYO3Un5aFNTzInqMs8aJCu/1R8gOuRkIcCVLI6iyMO4f5107eM= X-OriginatorOrg: opensource.altera.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Mar 2016 19:09:17.5643 (UTC) X-MS-Exchange-CrossTenant-Id: fbd72e03-d4a5-4110-adce-614d51f2077a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fbd72e03-d4a5-4110-adce-614d51f2077a; Ip=[66.35.236.236]; Helo=[sj-itexedge04.altera.priv.altera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0301MB1286 Sender: linux-hwmon-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thor Thayer Add the Altera Arria10 System Resource node. This is a Multi-Function device with GPIO and HWMON support. Signed-off-by: Thor Thayer --- arch/arm/boot/dts/socfpga_arria10.dtsi | 15 +++++++++++++++ arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 17 +++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 1c5e139..069b0a0 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -563,6 +563,21 @@ status = "disabled"; }; + spi1: spi@ffda5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda5000 0x100>; + interrupts = <0 102 4>; + num-chipselect = <4>; + bus-num = <0>; + /*32bit_access;*/ + tx-dma-channel = <&pdma 16>; + rx-dma-channel = <&pdma 17>; + clocks = <&spi_m_clk>; + status = "disabled"; + }; + sdr: sdr@ffc25000 { compatible = "syscon"; reg = <0xffcfb100 0x80>; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 567df98..095fd72 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -70,6 +70,23 @@ status = "okay"; }; +&spi1 { + status = "okay"; + + a10_sysres: a10_sysres@0 { + compatible = "altr,altr-a10sr"; + reg = <0>; + spi-max-frequency = <1000000>; + + a10sr_gpio: a10sr_gpio { + compatible = "altr,a10sr-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + }; + }; +}; + &i2c1 { speed-mode = <0>; status = "okay";