From patchwork Thu Jul 14 11:52:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 9229649 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BFAD66075D for ; Thu, 14 Jul 2016 12:00:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A6C5F264FB for ; Thu, 14 Jul 2016 12:00:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9B74B2815E; Thu, 14 Jul 2016 12:00:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 346B1264FB for ; Thu, 14 Jul 2016 12:00:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751021AbcGNMAM (ORCPT ); Thu, 14 Jul 2016 08:00:12 -0400 Received: from ssl.serverraum.org ([213.133.101.245]:41943 "EHLO ssl.serverraum.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750947AbcGNMAL (ORCPT ); Thu, 14 Jul 2016 08:00:11 -0400 X-Greylist: delayed 462 seconds by postgrey-1.27 at vger.kernel.org; Thu, 14 Jul 2016 08:00:10 EDT Received: from mwalle01.kse.adk.loc (unknown [194.25.174.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 589D922367; Thu, 14 Jul 2016 13:52:21 +0200 (CEST) Authentication-Results: ssl.serverraum.org; dmarc=none header.from=walle.cc DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1468497142; bh=w4f4kihu4OWqlAHg3GHgGpU6nBPmBalTQZJMpi/bG1s=; h=From:To:Cc:Subject:Date:From; b=ijCO+GwjYSvLzTKbO9/aHZPVVFONcmYJ0l/bv6hJIybpH5znzxIkjS+4M8N2XBC52 C5qPPJ4aedzZuQdQiEe7ZIBgEqUY8+9Uk9U7aBau/p/J7XsSTB1ulOQw9i1tXo9QgO f+1VY2EylTucO0Nc5W0w173Frftm21WyJgOV203w= From: Michael Walle To: Jean Delvare Cc: Guenter Roeck , linux-hwmon@vger.kernel.org, Rini , Michael Walle , stable@vger.kernel.org Subject: [PATCH] hwmon: adt7411: add rev5 workaround Date: Thu, 14 Jul 2016 13:52:07 +0200 Message-Id: <1468497127-6325-1-git-send-email-michael@walle.cc> X-Mailer: git-send-email 2.1.4 X-Virus-Scanned: clamav-milter 0.99.2 at web X-Virus-Status: Clean Sender: linux-hwmon-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Bit 3 in the CFG1 register has to be 1 to make AIN3 work properly since silicon revision 5. Although otherwise stated in the datasheet, the default value is not 1. Set it to 1 to make AIN3 work. Signed-off-by: Michael Walle Cc: stable@vger.kernel.org --- There was already submission back in 2010. https://www.spinics.net/lists/lm-sensors/msg29973.html I don't want to take the ownership, but there wasn't a reaction of the original author. Anyway, I want to answer the raised questions. > And what is the problem with this? And what's your hardware? ADT7411 silicon rev5 either forgot to default this bit to 1 or any earlier revision didn't care about it. But with rev5, this bit has to be set otherwise the AIN3 input returns garbage. > [two uses of adt7411_modify_bit()] > > This is inefficient: you read and write the same register twice in a > row. It would be much better to read it once, modify all bits and write > it once. This patch does it the same way. IMHO the small size of the change justifies the slight inefficiency in the one time probe. The other way you have to take the lock, add extra code for unlock in error cases etc. But of course its up to you to decide. I'm happy to provide another patch with read, modify both bits and write back the value. drivers/hwmon/adt7411.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/hwmon/adt7411.c b/drivers/hwmon/adt7411.c index 827c037..5ed9b11 100644 --- a/drivers/hwmon/adt7411.c +++ b/drivers/hwmon/adt7411.c @@ -30,6 +30,7 @@ #define ADT7411_REG_CFG1 0x18 #define ADT7411_CFG1_START_MONITOR (1 << 0) +#define ADT7411_CFG1_RESERVED_BIT3 (1 << 3) #define ADT7411_REG_CFG2 0x19 #define ADT7411_CFG2_DISABLE_AVG (1 << 5) @@ -296,6 +297,16 @@ static int adt7411_probe(struct i2c_client *client, mutex_init(&data->device_lock); mutex_init(&data->update_lock); + /* + * Silicon rev5 workaround, bit 3 has to be set, but unlike mentioned + * in the datasheet, this is not set by default. If this bit is not + * set, AIN3 won't work at all. + */ + ret = adt7411_modify_bit(client, ADT7411_REG_CFG1, + ADT7411_CFG1_RESERVED_BIT3, 1); + if (ret < 0) + return ret; + ret = adt7411_modify_bit(client, ADT7411_REG_CFG1, ADT7411_CFG1_START_MONITOR, 1); if (ret < 0)