From patchwork Thu Sep 22 13:37:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhang Rui X-Patchwork-Id: 12985121 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 867CEC6FA82 for ; Thu, 22 Sep 2022 13:35:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231487AbiIVNfE (ORCPT ); Thu, 22 Sep 2022 09:35:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231516AbiIVNfC (ORCPT ); Thu, 22 Sep 2022 09:35:02 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27E76760EF; Thu, 22 Sep 2022 06:35:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663853702; x=1695389702; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=zDRjOn0bNlzHygZ+Y/AQDCZ7jTp+MJset84jKlggh44=; b=Dig47Rh4igi2ufHozJ8YRt3f2k0xH4mskSCW/Bz4aL4udRGT5mL5h+oY 5prF5pTDzMZvLQyBKFzcNsEt2Ey3LpoAwqrMwHRWeA277e7ZKQzAv5YN9 K+Yh+nnuGk0MsRESF86NtYv36/mr7eHuYcqKlrZ8SCZwkin4P3fiiy7uM 0RJXKLA3M4LkOsMonSj2UT7myNJpMIw8cMqLwGDzKtVf6WpHqovVZnpc+ M1N4BbOemzDbhRpuKK1VxuwZ7RGmsMJjSnu3n1rozvFFKtRUvIOCMU9En TrpLfEMSjY1AQ7YOT+DdiMlhYBDgHRZMb3BgdplOzOrPL27uvoaSvduow A==; X-IronPort-AV: E=McAfee;i="6500,9779,10478"; a="297894097" X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="297894097" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2022 06:35:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="619793823" Received: from power-sh.sh.intel.com ([10.239.183.122]) by orsmga002.jf.intel.com with ESMTP; 22 Sep 2022 06:34:57 -0700 From: Zhang Rui To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-hwmon@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, corbet@lwn.net, fenghua.yu@intel.com, jdelvare@suse.com, linux@roeck-us.net, len.brown@intel.com, rui.zhang@intel.com Subject: [PATCH V3 1/8] perf/x86/intel/P4: Unify logic for detecting HT Date: Thu, 22 Sep 2022 21:37:53 +0800 Message-Id: <20220922133800.12918-2-rui.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220922133800.12918-1-rui.zhang@intel.com> References: <20220922133800.12918-1-rui.zhang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org Any value larger than 1 suggests HT is supported. Although smp_num_siblings cannot be larger than 2 on P4 platform, it is better to keep the logic consistent across the kernel. Reviewed-by: Len Brown Signed-off-by: Zhang Rui --- arch/x86/include/asm/perf_event_p4.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h index 94de1a05aeba..b14e9a20a7c0 100644 --- a/arch/x86/include/asm/perf_event_p4.h +++ b/arch/x86/include/asm/perf_event_p4.h @@ -189,7 +189,7 @@ static inline int p4_ht_active(void) static inline int p4_ht_thread(int cpu) { #ifdef CONFIG_SMP - if (smp_num_siblings == 2) + if (smp_num_siblings > 1) return cpu != cpumask_first(this_cpu_cpumask_var_ptr(cpu_sibling_map)); #endif return 0;