| Message ID | 20230712091241.3668454-3-Naresh.Solanki@9elements.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | [v2,1/3] peci: cpu: Add Intel Sapphire Rapids support | expand |
On 7/12/23 02:12, Naresh Solanki wrote: > From: Patrick Rudolph <patrick.rudolph@9elements.com> > > This patch extends the functionality of the hwmon (peci/dimmtemp) to > include support for Sapphire Rapids platform. > > Sapphire Rapids can accommodate up to 8 CPUs, each with 16 DIMMs. To > accommodate this configuration, the maximum supported DIMM count is > increased, and the corresponding Sapphire Rapids ID and threshold code > are added. > > The patch has been tested on a 4S system with 64 DIMMs installed. > Default thresholds are utilized for Sapphire Rapids, as accessing the > threshold requires accessing the UBOX device on Uncore bus 0, which can > only be achieved using MSR access. The non-PCI-compliant MMIO BARs are > not available for this purpose. > > Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> > Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Assuming this will be applied through the peci tree: Acked-by: Guenter Roeck <linux@roeck-us.net> > --- > Changes in V2: > - Update subject. > --- > drivers/hwmon/peci/dimmtemp.c | 24 +++++++++++++++++++++++- > 1 file changed, 23 insertions(+), 1 deletion(-) > > diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c > index ed968401f93c..edafbfd66fef 100644 > --- a/drivers/hwmon/peci/dimmtemp.c > +++ b/drivers/hwmon/peci/dimmtemp.c > @@ -30,8 +30,10 @@ > #define DIMM_IDX_MAX_ON_ICX 2 > #define CHAN_RANK_MAX_ON_ICXD 4 > #define DIMM_IDX_MAX_ON_ICXD 2 > +#define CHAN_RANK_MAX_ON_SPR 128 > +#define DIMM_IDX_MAX_ON_SPR 2 > > -#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX > +#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_SPR > #define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX > #define DIMM_NUMS_MAX (CHAN_RANK_MAX * DIMM_IDX_MAX) > > @@ -530,6 +532,15 @@ read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u > return 0; > } > > +static int > +read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data) > +{ > + /* Use defaults */ > + *data = (95 << 16) | (90 << 8); > + > + return 0; > +} > + > static const struct dimm_info dimm_hsx = { > .chan_rank_max = CHAN_RANK_MAX_ON_HSX, > .dimm_idx_max = DIMM_IDX_MAX_ON_HSX, > @@ -572,6 +583,13 @@ static const struct dimm_info dimm_icxd = { > .read_thresholds = &read_thresholds_icx, > }; > > +static const struct dimm_info dimm_spr = { > + .chan_rank_max = CHAN_RANK_MAX_ON_SPR, > + .dimm_idx_max = DIMM_IDX_MAX_ON_SPR, > + .min_peci_revision = 0x40, > + .read_thresholds = &read_thresholds_spr, > +}; > + > static const struct auxiliary_device_id peci_dimmtemp_ids[] = { > { > .name = "peci_cpu.dimmtemp.hsx", > @@ -597,6 +615,10 @@ static const struct auxiliary_device_id peci_dimmtemp_ids[] = { > .name = "peci_cpu.dimmtemp.icxd", > .driver_data = (kernel_ulong_t)&dimm_icxd, > }, > + { > + .name = "peci_cpu.dimmtemp.spr", > + .driver_data = (kernel_ulong_t)&dimm_spr, > + }, > { } > }; > MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids);
diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c index ed968401f93c..edafbfd66fef 100644 --- a/drivers/hwmon/peci/dimmtemp.c +++ b/drivers/hwmon/peci/dimmtemp.c @@ -30,8 +30,10 @@ #define DIMM_IDX_MAX_ON_ICX 2 #define CHAN_RANK_MAX_ON_ICXD 4 #define DIMM_IDX_MAX_ON_ICXD 2 +#define CHAN_RANK_MAX_ON_SPR 128 +#define DIMM_IDX_MAX_ON_SPR 2 -#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX +#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_SPR #define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX #define DIMM_NUMS_MAX (CHAN_RANK_MAX * DIMM_IDX_MAX) @@ -530,6 +532,15 @@ read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u return 0; } +static int +read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data) +{ + /* Use defaults */ + *data = (95 << 16) | (90 << 8); + + return 0; +} + static const struct dimm_info dimm_hsx = { .chan_rank_max = CHAN_RANK_MAX_ON_HSX, .dimm_idx_max = DIMM_IDX_MAX_ON_HSX, @@ -572,6 +583,13 @@ static const struct dimm_info dimm_icxd = { .read_thresholds = &read_thresholds_icx, }; +static const struct dimm_info dimm_spr = { + .chan_rank_max = CHAN_RANK_MAX_ON_SPR, + .dimm_idx_max = DIMM_IDX_MAX_ON_SPR, + .min_peci_revision = 0x40, + .read_thresholds = &read_thresholds_spr, +}; + static const struct auxiliary_device_id peci_dimmtemp_ids[] = { { .name = "peci_cpu.dimmtemp.hsx", @@ -597,6 +615,10 @@ static const struct auxiliary_device_id peci_dimmtemp_ids[] = { .name = "peci_cpu.dimmtemp.icxd", .driver_data = (kernel_ulong_t)&dimm_icxd, }, + { + .name = "peci_cpu.dimmtemp.spr", + .driver_data = (kernel_ulong_t)&dimm_spr, + }, { } }; MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids);