From patchwork Fri Jul 28 12:13:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 13331816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7254BC04A94 for ; Fri, 28 Jul 2023 12:16:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236581AbjG1MQV (ORCPT ); Fri, 28 Jul 2023 08:16:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234567AbjG1MPb (ORCPT ); Fri, 28 Jul 2023 08:15:31 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78C1949CC; Fri, 28 Jul 2023 05:13:24 -0700 (PDT) Message-ID: <20230728120931.448157949@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1690546402; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=v1jagm3qezJbhLi1KwbMq1PXX83lXTZZ+4TGqrP0z90=; b=OaTxVvEkBn8or9jvNdmQrVSkU7kbk6MdUYHBPqPvE3wbQk91EKdmBkdwW5cTUh0ohjVeZ/ 12rsXDyg/bDlbfRu5PQDd2wnvaxpTqYmed4W8xQCBeFIZeHfFqTxccMjm77jD4t/LmEE1g FzqGG24CYrpgWPN7yF8zMw0SMqm4PojNWv4ohANuHzeA3Li1O2Pe+7cmHFI1eZyI9awM4i 5KVSm+7/Ts4oVObTBC5T2vcvMjy6g7yyQdZBQnWV85yhhrZTdopob/PWtaIJvjWCOGAWBk g2OaccF3YJckfYJfKdtYSxcpKSvoS2/OGETHJUXA5WkQa0e7kFfVHE67BYw5qg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1690546402; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=v1jagm3qezJbhLi1KwbMq1PXX83lXTZZ+4TGqrP0z90=; b=vjKBc1lAvNSZpBzqQct6EMy+KlJwl47uNDI5KZB7JlhCw7KdOCBpBKMVBDQ/FCoheBWmal ewVNnLaHvO6uwXDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , "James E.J. Bottomley" , Dick Kennedy , James Smart , "Martin K. Petersen" , linux-scsi@vger.kernel.org, Guenter Roeck , linux-hwmon@vger.kernel.org, Jean Delvare , Huang Rui , Juergen Gross , Steve Wahl , Mike Travis , Dimitri Sivanich , Russ Anderson Subject: [patch v2 32/38] x86/mm/numa: Use core domain size on AMD References: <20230728105650.565799744@linutronix.de> MIME-Version: 1.0 Date: Fri, 28 Jul 2023 14:13:22 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-hwmon@vger.kernel.org cpuinfo::topo::x86_coreid_bits is about to be phased out. Use the core domain size from the topology information. Add a comment why the early MPTABLE parsing is required and decrapify the loop which sets the APIC ID to node map. Signed-off-by: Thomas Gleixner --- arch/x86/mm/amdtopology.c | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) --- a/arch/x86/mm/amdtopology.c +++ b/arch/x86/mm/amdtopology.c @@ -54,13 +54,11 @@ static __init int find_northbridge(void) int __init amd_numa_init(void) { - u64 start = PFN_PHYS(0); + unsigned int numnodes, cores, apicid; + u64 prevbase, start = PFN_PHYS(0); u64 end = PFN_PHYS(max_pfn); - unsigned numnodes; - u64 prevbase; - int i, j, nb; u32 nodeid, reg; - unsigned int bits, cores, apicid_base; + int i, j, nb; if (!early_pci_allowed()) return -EINVAL; @@ -158,26 +156,25 @@ int __init amd_numa_init(void) return -ENOENT; /* - * We seem to have valid NUMA configuration. Map apicids to nodes - * using the coreid bits from early_identify_cpu. + * We seem to have valid NUMA configuration. Map apicids to nodes + * using the size of the core domain in the APIC space. */ - bits = boot_cpu_data.x86_coreid_bits; - cores = 1 << bits; - apicid_base = 0; + cores = topology_get_domain_size(TOPO_CORE_DOMAIN); /* - * get boot-time SMP configuration: + * Scan MPTABLE to map the local APIC and ensure that the boot CPU + * APIC ID is valid. This is required because on pre ACPI/SRAT + * systems IO-APICs are mapped before the boot CPU. */ early_get_smp_config(); - if (boot_cpu_physical_apicid > 0) { - pr_info("BSP APIC ID: %02x\n", boot_cpu_physical_apicid); - apicid_base = boot_cpu_physical_apicid; + apicid = boot_cpu_physical_apicid; + if (apicid > 0) + pr_info("BSP APIC ID: %02x\n", apicid); + + for_each_node_mask(i, numa_nodes_parsed) { + for (j = 0; j < cores; j++, apicid++) + set_apicid_to_node(apicid, i); } - - for_each_node_mask(i, numa_nodes_parsed) - for (j = apicid_base; j < cores + apicid_base; j++) - set_apicid_to_node((i << bits) + j, i); - return 0; }