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[78.94.0.51]) by smtp.gmail.com with ESMTPSA id tj7-20020a170907c24700b00a413d1eda4bsm5039616ejc.87.2024.03.04.08.45.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Mar 2024 08:45:01 -0800 (PST) From: Naresh Solanki To: Guenter Roeck , Jean Delvare Cc: mazziesaccount@gmail.com, Patrick Rudolph , Naresh Solanki , linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] hwmon: (pmbus/mp2975) Fix IRQ masking Date: Mon, 4 Mar 2024 22:14:45 +0530 Message-ID: <20240304164446.4153915-1-naresh.solanki@9elements.com> X-Mailer: git-send-email 2.42.0 Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Patrick Rudolph The MP2971/MP2973 use a custom 16bit register format for SMBALERT_MASK which doesn't follow the PMBUS specification. Map the PMBUS defined bits used by the common code onto the custom format used by MPS and since the SMBALERT_MASK is currently never read by common code only implement the mapping for write transactions. Signed-off-by: Patrick Rudolph Signed-off-by: Naresh Solanki --- drivers/hwmon/pmbus/mp2975.c | 77 ++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) base-commit: 90d35da658da8cff0d4ecbb5113f5fac9d00eb72 diff --git a/drivers/hwmon/pmbus/mp2975.c b/drivers/hwmon/pmbus/mp2975.c index e5fa10b3b8bc..766026204d88 100644 --- a/drivers/hwmon/pmbus/mp2975.c +++ b/drivers/hwmon/pmbus/mp2975.c @@ -392,6 +392,82 @@ static int mp2973_read_word_data(struct i2c_client *client, int page, return ret; } +static int mp2973_write_word_data(struct i2c_client *client, int page, + int reg, u16 word) +{ + u8 target, mask; + int ret; + + if (reg != PMBUS_SMBALERT_MASK) + return -ENODATA; + + /* + * Vendor-specific SMBALERT_MASK register with 16 maskable bits. + */ + ret = pmbus_read_word_data(client, 0, 0, PMBUS_SMBALERT_MASK); + if (ret < 0) + return ret; + + target = word & 0xff; + mask = word >> 8; + +/* + * Set/Clear 'bit' in 'ret' based on condition followed by define for each bit in SMBALERT_MASK. + * Also bit 2 & 15 are reserved. + */ +#define SWAP(cond, bit) (ret = (mask & cond) ? (ret & ~BIT(bit)) : (ret | BIT(bit))) + +#define MP2973_TEMP_OT 0 +#define MP2973_VIN_UVLO 1 +#define MP2973_VIN_OVP 3 +#define MP2973_MTP_FAULT 4 +#define MP2973_OTHER_COMM 5 +#define MP2973_MTP_BLK_TRIG 6 +#define MP2973_PACKET_ERROR 7 +#define MP2973_INVALID_DATA 8 +#define MP2973_INVALID_COMMAND 9 +#define MP2973_IOUT_OC_LV 10 +#define MP2973_IOUT_OC 11 +#define MP2973_VOUT_MAX_MIN_WARNING 12 +#define MP2973_VOLTAGE_UV 13 +#define MP2973_VOLTAGE_OV 14 + + switch (target) { + case PMBUS_STATUS_CML: + SWAP(PB_CML_FAULT_INVALID_DATA, MP2973_INVALID_DATA); + SWAP(PB_CML_FAULT_INVALID_COMMAND, MP2973_INVALID_COMMAND); + SWAP(PB_CML_FAULT_OTHER_COMM, MP2973_OTHER_COMM); + SWAP(PB_CML_FAULT_PACKET_ERROR, MP2973_PACKET_ERROR); + break; + case PMBUS_STATUS_VOUT: + SWAP(PB_VOLTAGE_UV_FAULT, MP2973_VOLTAGE_UV); + SWAP(PB_VOLTAGE_OV_FAULT, MP2973_VOLTAGE_OV); + break; + case PMBUS_STATUS_IOUT: + SWAP(PB_IOUT_OC_FAULT, MP2973_IOUT_OC); + SWAP(PB_IOUT_OC_LV_FAULT, MP2973_IOUT_OC_LV); + break; + case PMBUS_STATUS_TEMPERATURE: + SWAP(PB_TEMP_OT_FAULT, MP2973_TEMP_OT); + break; + /* + * Map remaining bits to MFR specific to let the PMBUS core mask + * those bits by default. + */ + case PMBUS_STATUS_MFR_SPECIFIC: + SWAP(BIT(1), MP2973_VIN_UVLO); + SWAP(BIT(3), MP2973_VIN_OVP); + SWAP(BIT(4), MP2973_MTP_FAULT); + SWAP(BIT(6), MP2973_MTP_BLK_TRIG); + break; + default: + return 0; + } +#undef SWAP + + return pmbus_write_word_data(client, 0, PMBUS_SMBALERT_MASK, ret); +} + static int mp2975_read_word_data(struct i2c_client *client, int page, int phase, int reg) { @@ -907,6 +983,7 @@ static struct pmbus_driver_info mp2973_info = { PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP | PMBUS_HAVE_POUT | PMBUS_HAVE_PIN | PMBUS_HAVE_STATUS_INPUT, .read_word_data = mp2973_read_word_data, + .write_word_data = mp2973_write_word_data, #if IS_ENABLED(CONFIG_SENSORS_MP2975_REGULATOR) .num_regulators = 1, .reg_desc = mp2975_reg_desc,