From patchwork Thu Sep 12 07:08:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Akshay" X-Patchwork-Id: 13801527 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2065.outbound.protection.outlook.com [40.107.212.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1F29188930 for ; Thu, 12 Sep 2024 07:08:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.212.65 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124933; cv=fail; b=MS2GT1/EeYriXs2+9QCZjSEsPV1qNEI3q6lLXVULAIjw+zT2T6GtM2MAIX0pU9fl6SXjOBPdpdh/xcyr2BcJtTfBVWzoAqkDXdVr6wAFdNbz5Ek1i4vX1MJ3PL2bBI6JGNG4bJ5VqvyCwjm1BYJZjCrflKrZ1IKFcjpSlQaAxMo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726124933; c=relaxed/simple; bh=Q/F4dwtp8Ler1PY3K+KDzq8KKcCncrNRczWRPo6VxW4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lDf8soL4Qz09odOC24Cp5rNoYavo5to8jX4ATNFJtpk4R7pLz4EeaAcyErcWsOTG/9wcZPj5ToN19YS2GvGTvT6rfMbojxbRhyPtz5jB/nZzAxWYdA17esaWFP46sY/FMCFgbcJMyZujsCof6jXT3/+0FfvmpkfWZmHwzEEOGXo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=LOf7B829; arc=fail smtp.client-ip=40.107.212.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="LOf7B829" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=pM8Jvc6kcblAFUzUegOLmMX11Q24JbHpngsntfVtxtte3F0S1xzn0A1L2D77cuTnCl+sUqSyVV1l5mwIEnK4R73TpAm9+Sppvnfe1uVm1/HQ3Io6JBXl262MQgQMtZLd27nmkmuyecv3sQ8j7MDSjvAAwDkrEmAPttsmIbcTbTAXkvVYIKfi6U6s92fWRnBpB7O65NHIlZlD8tzfRsIv8/YaTfdh/4iFhTxIoeGBHRyQvVgW3wxWE1RlHconDdvd7yLR4ma/xcanomE1+QLLXwAzTZ3YlCSLK+jMMfcHeolQFcXOg/sYN9eiUblR8HIEYjne1fNWgI5RaysNZthRdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ssqRBtzFff9/wluJDRjUDPmvENR67sBQ+ZrRIwyD8Yk=; b=BgE0ibAP+QHAdJ69ORtfzXJxcugMf99R4/jmpLyO4ZtHqlWWDcf4Rl0+ktrqFG08Ts2wscKhdw62SFlfSMJ6NOvnW3GSpDgnwL9GQvcjqVy3bR8dhaMKDphybCc7vPs7zdUmpYcqOT7gFYh8pRNv+Rm+3pH6lECprYo3YE0l9TQvTrvILl5bNfWOlSAQVlwcwrmVlqT7Uva3k/81h/L0UNJUG/eou3StcVi1B65wfekPqjL8JRgD1y/RocjpeKUWtBC/OCxYdGa01uWjkuEm7OczxRUM/jY9kv3LY0mMabySn3vZ3lvhoVk8ufeNYisT0qGiSii9xRxbR+ig2X/dZw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ssqRBtzFff9/wluJDRjUDPmvENR67sBQ+ZrRIwyD8Yk=; b=LOf7B829PFo7KSwnRkFkOVs/QZqfqdXdLs/jv8ZBZKBCAg2/25/IpZcIlCY9UTwtUPmjXJwawJDQv0NQ3yWYwhG4C6u4uQRWf+etoo/7BZfkgOktYmfGghvGEVLFbDxlFTLBXdhURMNTEkCXw2r35cuCXMidmqVflj/9luORTeM= Received: from CH2PR08CA0015.namprd08.prod.outlook.com (2603:10b6:610:5a::25) by DM6PR12MB4403.namprd12.prod.outlook.com (2603:10b6:5:2ab::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.26; Thu, 12 Sep 2024 07:08:47 +0000 Received: from CH1PEPF0000AD7D.namprd04.prod.outlook.com (2603:10b6:610:5a:cafe::f0) by CH2PR08CA0015.outlook.office365.com (2603:10b6:610:5a::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7939.25 via Frontend Transport; Thu, 12 Sep 2024 07:08:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD7D.mail.protection.outlook.com (10.167.244.86) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Thu, 12 Sep 2024 07:08:46 +0000 Received: from amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Sep 2024 02:08:44 -0500 From: Akshay Gupta To: , CC: , , , , Akshay Gupta Subject: [PATCH v4 4/9] misc: amd-sbi: Add support for AMD_SBI IOCTL Date: Thu, 12 Sep 2024 07:08:05 +0000 Message-ID: <20240912070810.1644621-5-akshay.gupta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240912070810.1644621-1-akshay.gupta@amd.com> References: <20240912070810.1644621-1-akshay.gupta@amd.com> Precedence: bulk X-Mailing-List: linux-hwmon@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7D:EE_|DM6PR12MB4403:EE_ X-MS-Office365-Filtering-Correlation-Id: e9715915-4e50-4a07-b720-08dcd2f9bec7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: Cnvx9k8Jw+LYK8RRxOJJUnBfgPDS/p+sIFBGmY4KuqK2R2VANXxtN1UgZL6A9yRmvZD88vwh9Gb2L6mW+zNc29tALw54+r7XUyhdeXDImcucJTlyzK1Sc93yuVihQudKYhvY9/EYnrOS3tMqoZN7A8cdLvVx1/F3eLRDflxXsPj8JdWEh+gCw8EioWkqBWGATZsMQAMKgRcotr21Ip0mWQOVenKZvRB9VS6oK/tSza+Vj85QFYTr47VY4G9g2LDJzAh6bKnZ8PDuVVzT9SmZ58Xl7DmJrJXLEHz2KQ/S+VV3rS8E2FishCxDwD28g1A5y0T6pdXWKYfTqB3veoJoqFUM3X8sUpMAlBMZcAWZvN4xyQTeK/JXMcvyjdhZreUsZEdnseDxEyaCsOVcIFGt/SpS2E+v8XAn4YDmzCTiFf7/mfjS/PDA8XbfTcauSQWhWtkSlRDN1ooEI64+RxOBDvXWiqsgWYdTrAINiylaLy5c6bBu1woJDAQC6u6e0cjI7olv8bB3wSfDF/8G2x4MPeCzzACzcxc7qQlCdSe9jIKgeNtkSh30nOYROtNxDFiVNi6F2IrCItoLxwd8cQYlPNNwUxlLNb0099pCunfa0sqb/cO5xrAdoLJNmg0LCQoiGaBo521hfAtMNIr0o9rQ+YL03zVVAv2tP8gHybvY+55vP146N6oV3RLaiBwVuGlN6veFHy3hsm2qjOCzGwUJctzyCbjf2VCBCh+re5WQ0MpU4D/+A2qQfWqfTI17fcrvZvhkx0t+vP8dRVmzqONQ51KPRUQMg5P45GSZLp4ecWRdee5fr2ok15NhcuN1PYq0ek1Ce7/TZjrk3jK7aTV7E8UB7Xr2xXufXB/FylqfKs1m7bgFEBMbzSed6IJDcJu7dOrwjPqtUa0UWofI0VzmHwjs5q2IxScscYsQ7M9J3/MamWcMo9zfnnF8bSizjqagqNhYDaozDQ1jDVVT/IgCWodoheAygbtPnZea36UkJKqo4EmMN4izMYLQuqh96TbQguWbuRVT5qCaVvvy2lQA0Noxq8vjkXbUa8g4sOctP6kElzwPJW0G5rslg3LdSQxuvgrWrWsQ16WyvRhz6yIy2mD+iF4X6XMy3RyANFHoRwc0EFPqGIHuQfsX3ZYByHDmMWkrC57+5M5MHdxrYgN2BwU0xIp4qLKKj7Mk7Y4kcg661myFgMPFpVVWbniTykiYP7wx02kJkIOAWYqB7sf6c9/ZWgLKHS1p80hEpSQXqI82mnE3MHKI5IJjHIWkgoJRmxhlZ+uGYYcpxR9BPp2REdlVhc3g71D5LL6xsQqc/ivDk/Gh5LeLR0xr1+s3sVhXSVTAxFFTE5r6W9Zv7GDbFJ8GJIvgSbelkNGtvNHu0QShdTqI3CzC0GuQv+6fXxi+RK02HMo8AIhShXXGPHAWw4fYReaMQus7sFXg8Sv+1B0QXhbOwdqWBj/sUSgM91O9 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2024 07:08:46.8279 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9715915-4e50-4a07-b720-08dcd2f9bec7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4403 The present sbrmi module only support reporting power via hwmon. However, AMD data center range of processors support various system management functionality using custom protocols defined in Advanced Platform Management Link (APML) specification. Register a miscdevice, which creates a device /dev/sbrmiX with an IOCTL interface for the user space to invoke the APML Mailbox protocol, which is already defined in sbrmi_mailbox_xfer(). The APML protocols depend on a set of RMI registers. Having an IOCTL as a single entry point will help in providing synchronization among these protocols as multiple transactions on RMI register set may create race condition. Support for other protocols will be added in subsequent patches. Open-sourced and widely used https://github.com/amd/esmi_oob_library will continue to provide user-space programmable API. Signed-off-by: Akshay Gupta Reviewed-by: Naveen Krishna Chatradhi --- Changes since v3: - Previously patch 3 - Documentation and comments changes Changes since v2: - update the MACROS name as per feedback Changes since v1: - Previously patch 5 - Add IOCTL description in ioctl-number.rst - Split patch as per suggestion. Documentation/misc-devices/index.rst | 1 + .../userspace-api/ioctl/ioctl-number.rst | 2 + drivers/misc/amd-sbi/rmi-core.c | 89 +++++++++++++++++-- drivers/misc/amd-sbi/rmi-core.h | 16 ++-- drivers/misc/amd-sbi/rmi-hwmon.c | 15 ++-- drivers/misc/amd-sbi/rmi-i2c.c | 25 +++++- include/uapi/misc/amd-apml.h | 66 ++++++++++++++ 7 files changed, 186 insertions(+), 28 deletions(-) create mode 100644 include/uapi/misc/amd-apml.h diff --git a/Documentation/misc-devices/index.rst b/Documentation/misc-devices/index.rst index 8c5b226d8313..081e79415e38 100644 --- a/Documentation/misc-devices/index.rst +++ b/Documentation/misc-devices/index.rst @@ -12,6 +12,7 @@ fit into other categories. :maxdepth: 2 ad525x_dpot + amd-sbi apds990x bh1770glc c2port diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst index e91c0376ee59..5a189300efc5 100644 --- a/Documentation/userspace-api/ioctl/ioctl-number.rst +++ b/Documentation/userspace-api/ioctl/ioctl-number.rst @@ -388,6 +388,8 @@ Code Seq# Include File Comments 0xF8 all arch/x86/include/uapi/asm/amd_hsmp.h AMD HSMP EPYC system management interface driver +0xF9 00-0F uapi/misc/amd-apml.h AMD side band system management interface driver + 0xFD all linux/dm-ioctl.h 0xFE all linux/isst_if.h ==== ===== ======================================================= ================================================================ diff --git a/drivers/misc/amd-sbi/rmi-core.c b/drivers/misc/amd-sbi/rmi-core.c index 57f2915ac8d5..92d33d589bdc 100644 --- a/drivers/misc/amd-sbi/rmi-core.c +++ b/drivers/misc/amd-sbi/rmi-core.c @@ -7,7 +7,10 @@ */ #include #include +#include #include +#include +#include #include #include #include "rmi-core.h" @@ -22,7 +25,7 @@ #define TRIGGER_MAILBOX 0x01 int rmi_mailbox_xfer(struct sbrmi_data *data, - struct sbrmi_mailbox_msg *msg) + struct apml_message *msg) { unsigned int bytes; int i, ret; @@ -46,8 +49,8 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, * Command Data In[31:0] to SBRMI::InBndMsg_inst[4:1] * SBRMI_x3C(MSB):SBRMI_x39(LSB) */ - for (i = 0; i < 4; i++) { - byte = (msg->data_in >> i * 8) & 0xff; + for (i = 0; i < AMD_SBI_MB_DATA_SIZE; i++) { + byte = msg->data_in.reg_in[i]; ret = regmap_write(data->regmap, SBRMI_INBNDMSG1 + i, byte); if (ret < 0) goto exit_unlock; @@ -76,13 +79,13 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, * response Command Data Out[31:0] from SBRMI::OutBndMsg_inst[4:1] * {SBRMI_x34(MSB):SBRMI_x31(LSB)}. */ - if (msg->read) { - for (i = 0; i < 4; i++) { + if (msg->data_in.reg_in[AMD_SBI_RD_FLAG_INDEX]) { + for (i = 0; i < AMD_SBI_MB_DATA_SIZE; i++) { ret = regmap_read(data->regmap, SBRMI_OUTBNDMSG1 + i, &bytes); if (ret < 0) - goto exit_unlock; - msg->data_out |= bytes << i * 8; + break; + msg->data_out.reg_out[i] = bytes; } } @@ -92,8 +95,78 @@ int rmi_mailbox_xfer(struct sbrmi_data *data, */ ret = regmap_write(data->regmap, SBRMI_STATUS, sw_status | SW_ALERT_MASK); - exit_unlock: mutex_unlock(&data->lock); return ret; } + +static long sbrmi_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) +{ + int __user *arguser = (int __user *)arg; + struct apml_message msg = { 0 }; + bool read = false; + int ret = -EFAULT; + + struct sbrmi_data *data = container_of(fp->private_data, struct sbrmi_data, + sbrmi_misc_dev); + if (!data) + return -ENODEV; + + /* Copy the structure from user */ + if (copy_struct_from_user(&msg, sizeof(msg), arguser, + sizeof(struct apml_message))) + return ret; + + /* Is this a read/monitor/get request */ + if (msg.data_in.reg_in[AMD_SBI_RD_FLAG_INDEX]) + read = true; + + switch (msg.cmd) { + case 0 ... 0x999: + /* Mailbox protocol */ + ret = rmi_mailbox_xfer(data, &msg); + break; + default: + pr_err("Command:0x%x not recognized\n", msg.cmd); + break; + } + + /* Copy results back to user only for get/monitor commands and firmware failures */ + if ((read && !ret) || ret == -EPROTOTYPE) { + if (copy_to_user(arguser, &msg, sizeof(struct apml_message))) + ret = -EFAULT; + } + return ret; +} + +static const struct file_operations sbrmi_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = sbrmi_ioctl, + .compat_ioctl = sbrmi_ioctl, +}; + +int create_misc_rmi_device(struct sbrmi_data *data, + struct device *dev) +{ + int ret; + + data->sbrmi_misc_dev.name = devm_kasprintf(dev, + GFP_KERNEL, + "sbrmi-%x", + data->dev_static_addr); + data->sbrmi_misc_dev.minor = MISC_DYNAMIC_MINOR; + data->sbrmi_misc_dev.fops = &sbrmi_fops; + data->sbrmi_misc_dev.parent = dev; + data->sbrmi_misc_dev.nodename = devm_kasprintf(dev, + GFP_KERNEL, + "sbrmi-%x", + data->dev_static_addr); + data->sbrmi_misc_dev.mode = 0600; + + ret = misc_register(&data->sbrmi_misc_dev); + if (ret) + return ret; + + dev_info(dev, "register %s device\n", data->sbrmi_misc_dev.name); + return ret; +} diff --git a/drivers/misc/amd-sbi/rmi-core.h b/drivers/misc/amd-sbi/rmi-core.h index 24a6957c8fa0..b728f5582256 100644 --- a/drivers/misc/amd-sbi/rmi-core.h +++ b/drivers/misc/amd-sbi/rmi-core.h @@ -6,10 +6,12 @@ #ifndef _SBRMI_CORE_H_ #define _SBRMI_CORE_H_ +#include #include #include #include #include +#include /* SB-RMI registers */ enum sbrmi_reg { @@ -48,19 +50,15 @@ enum sbrmi_msg_id { /* Each client has this additional data */ struct sbrmi_data { + struct miscdevice sbrmi_misc_dev; struct regmap *regmap; + /* Mutex locking */ struct mutex lock; - struct platform_device *pdev; u32 pwr_limit_max; + u8 dev_static_addr; }; -struct sbrmi_mailbox_msg { - u8 cmd; - bool read; - u32 data_in; - u32 data_out; -}; - -int rmi_mailbox_xfer(struct sbrmi_data *data, struct sbrmi_mailbox_msg *msg); +int rmi_mailbox_xfer(struct sbrmi_data *data, struct apml_message *msg); int create_hwmon_sensor_device(struct device *dev, struct sbrmi_data *data); +int create_misc_rmi_device(struct sbrmi_data *data, struct device *dev); #endif /*_SBRMI_CORE_H_*/ diff --git a/drivers/misc/amd-sbi/rmi-hwmon.c b/drivers/misc/amd-sbi/rmi-hwmon.c index 36913f105eef..5f1634a17579 100644 --- a/drivers/misc/amd-sbi/rmi-hwmon.c +++ b/drivers/misc/amd-sbi/rmi-hwmon.c @@ -6,6 +6,7 @@ */ #include #include +#include #include "rmi-core.h" /* Do not allow setting negative power limit */ @@ -15,7 +16,7 @@ static int sbrmi_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long *val) { struct sbrmi_data *data = dev_get_drvdata(dev); - struct sbrmi_mailbox_msg msg = { 0 }; + struct apml_message msg = { 0 }; int ret; if (!data) @@ -24,7 +25,7 @@ static int sbrmi_read(struct device *dev, enum hwmon_sensor_types type, if (type != hwmon_power) return -EINVAL; - msg.read = true; + msg.data_in.reg_in[AMD_SBI_RD_FLAG_INDEX] = 1; switch (attr) { case hwmon_power_input: msg.cmd = SBRMI_READ_PKG_PWR_CONSUMPTION; @@ -35,7 +36,7 @@ static int sbrmi_read(struct device *dev, enum hwmon_sensor_types type, ret = rmi_mailbox_xfer(data, &msg); break; case hwmon_power_cap_max: - msg.data_out = data->pwr_limit_max; + msg.data_out.mb_out[AMD_SBI_RD_WR_DATA_INDEX] = data->pwr_limit_max; ret = 0; break; default: @@ -44,7 +45,7 @@ static int sbrmi_read(struct device *dev, enum hwmon_sensor_types type, if (ret < 0) return ret; /* hwmon power attributes are in microWatt */ - *val = (long)msg.data_out * 1000; + *val = (long)msg.data_out.mb_out[AMD_SBI_RD_WR_DATA_INDEX] * 1000; return ret; } @@ -52,7 +53,7 @@ static int sbrmi_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, long val) { struct sbrmi_data *data = dev_get_drvdata(dev); - struct sbrmi_mailbox_msg msg = { 0 }; + struct apml_message msg = { 0 }; if (!data) return -ENODEV; @@ -68,8 +69,8 @@ static int sbrmi_write(struct device *dev, enum hwmon_sensor_types type, val = clamp_val(val, SBRMI_PWR_MIN, data->pwr_limit_max); msg.cmd = SBRMI_WRITE_PKG_PWR_LIMIT; - msg.data_in = val; - msg.read = false; + msg.data_in.mb_in[AMD_SBI_RD_WR_DATA_INDEX] = val; + msg.data_in.reg_in[AMD_SBI_RD_FLAG_INDEX] = 0; return rmi_mailbox_xfer(data, &msg); } diff --git a/drivers/misc/amd-sbi/rmi-i2c.c b/drivers/misc/amd-sbi/rmi-i2c.c index c4207672d1e4..0e80acc61d6e 100644 --- a/drivers/misc/amd-sbi/rmi-i2c.c +++ b/drivers/misc/amd-sbi/rmi-i2c.c @@ -40,15 +40,15 @@ static int sbrmi_enable_alert(struct sbrmi_data *data) static int sbrmi_get_max_pwr_limit(struct sbrmi_data *data) { - struct sbrmi_mailbox_msg msg = { 0 }; + struct apml_message msg = { 0 }; int ret; msg.cmd = SBRMI_READ_PKG_MAX_PWR_LIMIT; - msg.read = true; + msg.data_in.reg_in[AMD_SBI_RD_FLAG_INDEX] = 1; ret = rmi_mailbox_xfer(data, &msg); if (ret < 0) return ret; - data->pwr_limit_max = msg.data_out; + data->pwr_limit_max = msg.data_out.mb_out[AMD_SBI_RD_WR_DATA_INDEX]; return ret; } @@ -83,8 +83,24 @@ static int sbrmi_i2c_probe(struct i2c_client *client) if (ret < 0) return ret; + data->dev_static_addr = client->addr; dev_set_drvdata(dev, data); - return create_hwmon_sensor_device(dev, data); + ret = create_hwmon_sensor_device(dev, data); + if (ret < 0) + return ret; + return create_misc_rmi_device(data, dev); +} + +static void sbrmi_i2c_remove(struct i2c_client *client) +{ + struct sbrmi_data *data = dev_get_drvdata(&client->dev); + + misc_deregister(&data->sbrmi_misc_dev); + /* Assign fops and parent of misc dev to NULL */ + data->sbrmi_misc_dev.fops = NULL; + data->sbrmi_misc_dev.parent = NULL; + dev_info(&client->dev, "Removed sbrmi-i2c driver\n"); + return; } static const struct i2c_device_id sbrmi_id[] = { @@ -107,6 +123,7 @@ static struct i2c_driver sbrmi_driver = { .of_match_table = of_match_ptr(sbrmi_of_match), }, .probe = sbrmi_i2c_probe, + .remove = sbrmi_i2c_remove, .id_table = sbrmi_id, }; diff --git a/include/uapi/misc/amd-apml.h b/include/uapi/misc/amd-apml.h new file mode 100644 index 000000000000..dc926327629d --- /dev/null +++ b/include/uapi/misc/amd-apml.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Copyright (C) 2021-2024 Advanced Micro Devices, Inc. + */ +#ifndef _AMD_APML_H_ +#define _AMD_APML_H_ + +#include + +/* These are byte indexes into data_in and data_out arrays */ +#define AMD_SBI_RD_WR_DATA_INDEX 0 +#define AMD_SBI_REG_OFF_INDEX 0 +#define AMD_SBI_REG_VAL_INDEX 4 +#define AMD_SBI_RD_FLAG_INDEX 7 + +#define AMD_SBI_MB_DATA_SIZE 4 + +struct apml_message { + /* message ids: + * Mailbox Messages: 0x0 ... 0x999 + */ + __u32 cmd; + + /* + * 8 bit data for reg read, + * 32 bit data in case of mailbox, + */ + union { + __u32 mb_out[2]; + __u8 reg_out[8]; + } data_out; + + /* + * [0]...[3] mailbox 32bit input + * [7] read/write functionality + */ + union { + __u32 mb_in[2]; + __u8 reg_in[8]; + } data_in; +} __attribute__((packed)); + +/** + * AMD sideband interface base IOCTL + */ +#define SB_BASE_IOCTL_NR 0xF9 + +/** + * DOC: SBRMI_IOCTL_CMD + * + * @Parameters + * + * @struct apml_message * + * Pointer to the &struct apml_message that will contain the protocol + * information + * + * @Description + * IOCTL command for APML messages using generic _IOWR + * The IOCTL provides userspace access to AMD sideband protocols + * The APML RMI module checks whether the cmd is + * - Mailbox message read/write(0x0~0x999) + * - returning "-EFAULT" if none of the above + */ +#define SBRMI_IOCTL_CMD _IOWR(SB_BASE_IOCTL_NR, 0, struct apml_message) + +#endif /*_AMD_APML_H_*/