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([10.237.72.59]) by orviesa001.jf.intel.com with ESMTP; 28 Feb 2025 06:18:05 -0800 From: Jarkko Nikula To: linux-i3c@lists.infradead.org Cc: Alexandre Belloni , Frank Li , Jarkko Nikula Subject: [PATCH 1/4] i3c: mipi-i3c-hci: Allow only relevant INTR_STATUS bit updates Date: Fri, 28 Feb 2025 16:17:59 +0200 Message-ID: <20250228141802.1344453-1-jarkko.nikula@linux.intel.com> X-Mailer: git-send-email 2.47.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250228_061809_438890_E2E81CAE X-CRM114-Status: GOOD ( 10.98 ) X-BeenThere: linux-i3c@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-i3c" Errors-To: linux-i3c-bounces+linux-i3c=archiver.kernel.org@lists.infradead.org Since MIPI I3C HCI specification version v0.8 INTR_STATUS bits 9:0 are reserved. Version v0.5 has bits 9 and 5:0 in use but not handled by the current driver code and not needed in DMA transfers. PIO transfers with v0.5 would require changes to both core.c: i3c_hci_irq_handler() and pio.c: hci_pio_irq_handler() though. For these reasons don't enable signal updates from INTR_STATUS bits 9:0. This change is a no-op for specification versions v0.8 and beyond but gets rid of "unexpected INTR_STATUS" errors if somebody (read me) wants to run code on old v0.5 IP version. Signed-off-by: Jarkko Nikula --- drivers/i3c/master/mipi-i3c-hci/core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mipi-i3c-hci/core.c index a71226d7ca59..e139d7e4d252 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -699,9 +699,10 @@ static int i3c_hci_init(struct i3c_hci *hci) if (ret) return -ENXIO; - /* Disable all interrupts and allow all signal updates */ + /* Disable all interrupts */ reg_write(INTR_SIGNAL_ENABLE, 0x0); - reg_write(INTR_STATUS_ENABLE, 0xffffffff); + /* Allow signal updates relevant to IP versions 0.8 and beyond */ + reg_write(INTR_STATUS_ENABLE, GENMASK(31, 10)); /* Make sure our data ordering fits the host's */ regval = reg_read(HC_CONTROL);