From patchwork Thu Sep 21 01:26:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "zhiyong.tao" X-Patchwork-Id: 9963147 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 607AA6056A for ; Thu, 21 Sep 2017 01:27:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 52344201F3 for ; Thu, 21 Sep 2017 01:27:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 45B602625B; Thu, 21 Sep 2017 01:27:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D57DD201F3 for ; Thu, 21 Sep 2017 01:27:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751343AbdIUB1G (ORCPT ); Wed, 20 Sep 2017 21:27:06 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:14359 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751000AbdIUB1F (ORCPT ); Wed, 20 Sep 2017 21:27:05 -0400 X-UUID: e3692fb2f3814682a563e3cd4cd467c7-20170921 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1990292478; Thu, 21 Sep 2017 09:27:01 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 21 Sep 2017 09:27:06 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 21 Sep 2017 09:27:19 +0800 From: Zhiyong Tao To: , , , , CC: , , , , , , , , , , , , Zhiyong Tao Subject: [PATCH 3/3] arm64: dts: mt2712: Add auxadc device node. Date: Thu, 21 Sep 2017 09:26:52 +0800 Message-ID: <1505957212-13402-4-git-send-email-zhiyong.tao@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1505957212-13402-1-git-send-email-zhiyong.tao@mediatek.com> References: <1505957212-13402-1-git-send-email-zhiyong.tao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-iio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add auxadc device node for MT2712. Signed-off-by: Zhiyong Tao --- This patch dependents on "Mediatek MT2712 clock and scpsys support"[1]. Please accept this patch together with [1]. [1]http://lists.infradead.org/pipermail/linux-mediatek/2017-September/010461.html --- arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 4 ++++ arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 9 +++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index 14163b9..76cbf4a 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -28,6 +28,10 @@ }; }; +&auxadc { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 3232e4e..bf65c92 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -225,6 +225,15 @@ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; }; + auxadc: adc@11001000 { + compatible = "mediatek,mt2712-auxadc"; + reg = <0 0x11001000 0 0x1000>; + clocks = <&pericfg CLK_PERI_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + uart0: serial@11002000 { compatible = "mediatek,mt2712-uart", "mediatek,mt6577-uart";