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Wed, 18 Dec 2019 16:24:03 +0000 From: To: , , CC: , , , , , , , , Subject: [PATCH 06/10] iio: adc: at91-sama5d2_adc: handle unfinished conversions Thread-Topic: [PATCH 06/10] iio: adc: at91-sama5d2_adc: handle unfinished conversions Thread-Index: AQHVtb+OsZRnT6XyDEmDjlFvS26mBg== Date: Wed, 18 Dec 2019 16:24:01 +0000 Message-ID: <1576686157-11939-7-git-send-email-eugen.hristev@microchip.com> References: <1576686157-11939-1-git-send-email-eugen.hristev@microchip.com> In-Reply-To: <1576686157-11939-1-git-send-email-eugen.hristev@microchip.com> Accept-Language: en-US, ro-RO Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: dc5c8436-1abf-4358-d823-08d783d6b21f x-ms-traffictypediagnostic: DM5PR11MB1769: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; x-forefront-prvs: 0255DF69B9 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(366004)(396003)(39860400002)(136003)(346002)(376002)(199004)(189003)(66476007)(66946007)(66446008)(76116006)(91956017)(2616005)(64756008)(66556008)(86362001)(186003)(316002)(110136005)(8676002)(54906003)(8936002)(71200400001)(81166006)(478600001)(2906002)(6512007)(26005)(81156014)(36756003)(4326008)(6506007)(5660300002)(6486002)(107886003);DIR:OUT;SFP:1101;SCL:1;SRVR:DM5PR11MB1769;H:DM5PR11MB1242.namprd11.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: bCkJtutP0xy68E4acZfq30j4VmYN2Nq+46TvoZU20ewDRoXLjMQgT8LrMOluBNkOyN8L5EYI3QRMyzuGLBss6pYdvjK9JjAUvlkBCRpTs/viIX8FgbFHmpzDEty4ZtadG1sGI2ABtsjCIHstb0YrtI+oYwT+p15SZ5wsitlYXJ6dOCyv+O6V1CFWbWNEUA1GJoKDkl9boHmf9IgnNtOds6KxRn+FwFS/kR3nUCV5R1kEwPLJAe0VbnP7+t5SgO3RLPmbYuIukLn/OVdaAIEa7on/qqpb4DtD/9t3WSUhqAWoxYextHhtUbizjzWyy6K55k+wfHFwpuM6h6bEafPoROCFMtShVgvYXZGb2eG8gI9wH42LNOkhLoaxLkXdS3ZkE0v4wso5a/Acr4bdMaiFblXypcd9H9o7qcD9N16gJTVw+nFI8UcNTwnpzDZ3UhMU MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: dc5c8436-1abf-4358-d823-08d783d6b21f X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Dec 2019 16:24:01.5143 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: G660RjdCDbWxNRYwl49ps7IP40kT02FrxHff87XVFsM/VCHlTE3pYI9B3JGcmNuBnbaPfexSBvi7bmQ2CcgFsUqpoxdXSeAHHM1QvUAgSy8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB1769 Sender: linux-iio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Eugen Hristev It can happen that on IRQ trigger, not all conversions are done if we are enabling multiple channels. The IRQ is triggered on first EOC (end of channel), but it can happen that not all channels are done. This leads into erroneous reports to userspace (zero values or previous values). To solve this, in trigger handler, check if the mask of done channels is the same as the mask of active scan channels. If it's the same, proceed and push to buffers. Otherwise, to avoid sleeping in trigger handler, start a workq that will wait until all channels are ready. Normally, it should happen that in a short time fashion, all channels are ready, since the first IRQ triggered. The workq can stall in a loop if a hardware fault happens (for example the clock suddently dissappears), but if it's a hardware fault then even exiting the workq won't fix the hardware. Signed-off-by: Eugen Hristev --- drivers/iio/adc/at91-sama5d2_adc.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index c575970..a6b4dff 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -487,6 +488,21 @@ static inline int at91_adc_of_xlate(struct iio_dev *indio_dev, return at91_adc_chan_xlate(indio_dev, iiospec->args[0]); } +static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev) +{ + u32 mask = 0; + u8 bit; + + for_each_set_bit(bit, indio_dev->active_scan_mask, + indio_dev->num_channels) { + struct iio_chan_spec const *chan = + at91_adc_chan_get(indio_dev, bit); + mask |= BIT(chan->channel); + } + + return mask & GENMASK(11, 0); +} + static void at91_adc_config_emr(struct at91_adc_state *st) { /* configure the extended mode register */ @@ -1044,12 +1060,13 @@ static int at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev, struct iio_poll_func *pf) { struct at91_adc_state *st = iio_priv(indio_dev); + u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev); /* * Check if the conversion is ready. If not, schedule a work to * check again later. */ - if (!(at91_adc_readl(st, AT91_SAMA5D2_ISR) & GENMASK(11, 0))) { + if ((at91_adc_readl(st, AT91_SAMA5D2_ISR) & mask) != mask) { schedule_work(&st->workq); return -EINPROGRESS; } @@ -1269,9 +1286,13 @@ static void at91_adc_workq_handler(struct work_struct *workq) struct at91_adc_state *st = container_of(workq, struct at91_adc_state, workq); struct iio_dev *indio_dev = iio_priv_to_dev(st); + u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev); if ((indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES) && iio_trigger_validate_own_device(indio_dev->trig, indio_dev)) { + while ((at91_adc_readl(st, AT91_SAMA5D2_ISR) & mask) != mask) + udelay(1); + at91_adc_read_and_push_channels(indio_dev, st->timestamp); iio_trigger_notify_done(indio_dev->trig); } else {