From patchwork Fri Jan 10 16:18:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 11327933 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 61C0814B4 for ; Fri, 10 Jan 2020 16:19:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4610720673 for ; Fri, 10 Jan 2020 16:19:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728948AbgAJQTv (ORCPT ); Fri, 10 Jan 2020 11:19:51 -0500 Received: from esa3.microchip.iphmx.com ([68.232.153.233]:17028 "EHLO esa3.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728549AbgAJQTu (ORCPT ); Fri, 10 Jan 2020 11:19:50 -0500 Received-SPF: Pass (esa3.microchip.iphmx.com: domain of Claudiu.Beznea@microchip.com designates 198.175.253.82 as permitted sender) identity=mailfrom; client-ip=198.175.253.82; receiver=esa3.microchip.iphmx.com; envelope-from="Claudiu.Beznea@microchip.com"; x-sender="Claudiu.Beznea@microchip.com"; x-conformance=spf_only; x-record-type="v=spf1"; x-record-text="v=spf1 mx a:ushub1.microchip.com a:smtpout.microchip.com -exists:%{i}.spf.microchip.iphmx.com include:servers.mcsv.net include:mktomail.com include:spf.protection.outlook.com ~all" Received-SPF: None (esa3.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@email.microchip.com) identity=helo; client-ip=198.175.253.82; receiver=esa3.microchip.iphmx.com; envelope-from="Claudiu.Beznea@microchip.com"; x-sender="postmaster@email.microchip.com"; x-conformance=spf_only Authentication-Results: esa3.microchip.iphmx.com; dkim=none (message not signed) header.i=none; spf=Pass smtp.mailfrom=Claudiu.Beznea@microchip.com; spf=None smtp.helo=postmaster@email.microchip.com; dmarc=pass (p=none dis=none) d=microchip.com IronPort-SDR: QW++98HUTZR2sVb+Iv+KSuccKc0h/lmoJM6J3R8h8rer/siF1+6YHizeum0pvYJxppkudT4uro XzAwH/85mWIkuYl23xdst5remiUzqGIv8iHgpU8AKiE1K4gpPRMq92xMfgoFN3tqN1SoHp7GkH PGUOXhn14CxZWpow40WnC8v7n/fY1sFSlk8cd4yJYW6X8YJdkN3Tlm/2nxcXt1LcMoVwKpgwXY FaK7w6MKr7gvdF7yHaLDaLuNwlsQTLYTgRCgE+dfMbMrAF2gWnDtdSZ3o4C3dzPrgXgy8JKIQa ia8= X-IronPort-AV: E=Sophos;i="5.69,417,1571727600"; d="scan'208";a="62890441" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 10 Jan 2020 09:19:48 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 10 Jan 2020 09:19:47 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.85.251) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Fri, 10 Jan 2020 09:19:40 -0700 From: Claudiu Beznea To: , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , Claudiu Beznea Subject: [PATCH v2 08/17] dt-bindings: atmel-nand: add microchip,sam9x60-pmecc Date: Fri, 10 Jan 2020 18:18:00 +0200 Message-ID: <1578673089-3484-9-git-send-email-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1578673089-3484-1-git-send-email-claudiu.beznea@microchip.com> References: <1578673089-3484-1-git-send-email-claudiu.beznea@microchip.com> MIME-Version: 1.0 Sender: linux-iio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Add microchip,sam9x60-pmecc to DT bindings documentation. Signed-off-by: Claudiu Beznea Reviewed-by: Miquel Raynal Acked-by: Rob Herring --- Documentation/devicetree/bindings/mtd/atmel-nand.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt index 68b51dc58816..3aa297c97ab6 100644 --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt @@ -57,6 +57,7 @@ Required properties: "atmel,at91sam9g45-pmecc" "atmel,sama5d4-pmecc" "atmel,sama5d2-pmecc" + "microchip,sam9x60-pmecc" - reg: should contain 2 register ranges. The first one is pointing to the PMECC block, and the second one to the PMECC_ERRLOC block.