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Tue, 28 Jan 2020 12:57:39 +0000 From: To: , , CC: , , , Subject: [PATCH v3 1/3] iio: adc: at91-sama5d2_adc: fix differential channels in triggered mode Thread-Topic: [PATCH v3 1/3] iio: adc: at91-sama5d2_adc: fix differential channels in triggered mode Thread-Index: AQHV1dqFsAVAQA8Fs0errk5mUZMqBQ== Date: Tue, 28 Jan 2020 12:57:39 +0000 Message-ID: <1580216189-27418-2-git-send-email-eugen.hristev@microchip.com> References: <1580216189-27418-1-git-send-email-eugen.hristev@microchip.com> In-Reply-To: <1580216189-27418-1-git-send-email-eugen.hristev@microchip.com> Accept-Language: en-US, ro-RO Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6a63857a-64e2-4f02-7487-08d7a3f1a828 x-ms-traffictypediagnostic: DM5PR11MB1852: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6430; x-forefront-prvs: 029651C7A1 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(376002)(366004)(39860400002)(136003)(396003)(346002)(199004)(189003)(6512007)(2616005)(107886003)(76116006)(54906003)(91956017)(110136005)(66446008)(64756008)(66556008)(66476007)(66946007)(316002)(8936002)(6486002)(186003)(5660300002)(71200400001)(81156014)(4326008)(2906002)(81166006)(478600001)(36756003)(86362001)(6506007)(8676002)(26005);DIR:OUT;SFP:1101;SCL:1;SRVR:DM5PR11MB1852;H:DM5PR11MB1242.namprd11.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: D9v1GP1jHW7pkckk6TpB0x9xvNnqzZ0hqKcsjetnp6GSU0W7etIxqlDVzF78fwdMGYB+SuCfWqazvr1DlElqBW5E8+C9iAqeVVhlf2gF3YcudjLyv+FlSB+ruDDJHv6QgTAa4cmHeDV0+iYhL3PBFiNOHKgFYjhesyDYSwwhZ3rNR3JH3gWU49hkBHTlRkxFyxJart7LR/gjbb+gi+2mD0M6l535vbqCyNrAltvv0SusccfS3CwlI/P1MHUdwE9XzPMDwzIkolyQCJn2DRiNEZN28j6jJjHBTaKm5zihqMKKj+q6YObJX9cxjjJKTmxp+GbwXvxTT2yD2igI8Gp5/sbaH2zCaq8f93jgUCv7LJhlMYizb4gcu2ZZ/MdQTSdfqRJED9R1K22G3mqGw5gABew/P/iRNS/Ct1szTgSJI7XTHIIct0RlJzKmlqLCsQsr x-ms-exchange-antispam-messagedata: 9AY+Bx5MYs+vHQ0q6HeILb6dkKCPdQ465C1VgesBGb6xtoo79RNZIF8dze1AMYa+KX5vNse7ARAdns+eYqvoJ8SttqWHv84w8OSMl6Y4Nkp0Was6ltLMt6lUD7wzjghaHBaXpORnIjye073QcKLRCA== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 6a63857a-64e2-4f02-7487-08d7a3f1a828 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Jan 2020 12:57:39.5985 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Qk4/eNQTMfkWPQhlRuZ7uFm73d6K6Ra9C280mI7lnLxw8uyUEjNNwycKRdXJ52cIrNYmtcvXLuxr1NCVA7dTKZBkvLULZwhBKY50zxaFWnw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB1852 Sender: linux-iio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Eugen Hristev The differential channels require writing the channel offset register (COR). Otherwise they do not work in differential mode. The configuration of COR is missing in triggered mode. Fixes: 5e1a1da0f8c9 ("iio: adc: at91-sama5d2_adc: add hw trigger and buffer support") Signed-off-by: Eugen Hristev --- Changes in v2: - moved to the start of the list drivers/iio/adc/at91-sama5d2_adc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index e1850f3..2a6950a 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -723,6 +723,7 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) { struct iio_chan_spec const *chan = at91_adc_chan_get(indio, bit); + u32 cor; if (!chan) continue; @@ -732,6 +733,20 @@ static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) continue; if (state) { + cor = at91_adc_readl(st, AT91_SAMA5D2_COR); + + if (chan->differential) + cor |= (BIT(chan->channel) | + BIT(chan->channel2)) << + AT91_SAMA5D2_COR_DIFF_OFFSET; + else + cor &= ~(BIT(chan->channel) << + AT91_SAMA5D2_COR_DIFF_OFFSET); + + at91_adc_writel(st, AT91_SAMA5D2_COR, cor); + } + + if (state) { at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); /* enable irq only if not using DMA */