From patchwork Tue Oct 31 02:12:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 10033551 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BF35D60291 for ; Tue, 31 Oct 2017 02:12:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AD1AA28A01 for ; Tue, 31 Oct 2017 02:12:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A1BE028A04; Tue, 31 Oct 2017 02:12:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7700C28A01 for ; Tue, 31 Oct 2017 02:12:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752919AbdJaCMb (ORCPT ); Mon, 30 Oct 2017 22:12:31 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:45517 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752028AbdJaCMa (ORCPT ); Mon, 30 Oct 2017 22:12:30 -0400 Received: by mail-pf0-f194.google.com with SMTP id d28so12544648pfe.2; Mon, 30 Oct 2017 19:12:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=Xumi80fZ2we6qTzyXX7JEY3acJ1H8uDLIm7vDp5I7FI=; b=otqgc8SpYFNcUPZpRlNUR01vCTuP4Iqr/ZG6HVZpD5ynNVNc1A3vhl9hWz4b/vFTc+ 05D2j3GhM5kreG+jxv7d/EDb+4jd9N3qqr2FnlXLtdeem2LjvwUwnthsX+YGTrNsG+MC QlSUpvfksSRjMLfuXxU3DVLuKk88ievq1iTD234DyF8rh6hXlzOYZF+qMGQpBIK1BSwB a60k7et/K1epNYjLby3EfdYGLhu24GrXW6PtGUuQQZN1oVgr6AcSd5KoK9WX4J/6xj9h qPfOhBYN5aFYhTbbQcP3JZtm3Pc6pCD2tI8idQ3tJXaCLgiLMfi7W2BXBpJhY7X4gTpW 3hKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=Xumi80fZ2we6qTzyXX7JEY3acJ1H8uDLIm7vDp5I7FI=; b=ncE/s1em8aIOPRjtK7nzmeCAK7n1OBhLR07XRrdp/Pt9pr3QgvM0xypajcSO+rYpHP tcOZ82i3XAmE9IRq3fAI3yeHoZyJEUW0uaLRTgSfLAy7zC+jj1rZml06BTARPSxZJBlD 0pGOjhvqFnJlQHmrRwlrRYmJT4MDDxBPabGXht5tiDhjegaP62QNhfcBJDqE5kRai5WV NfHnV9yT553NBvS4xruvpEu/X50WnAqnbdi8L7ki9PfuxfYWQEfdz+2JnL/6f9aa6cTQ MfdFEmOgkZv5JATwvYnrWdso7lvnV3iga1MX2M3bPNFlqWaE0iV+YBQFEhxFYwoLIkbP yJOQ== X-Gm-Message-State: AMCzsaWI4vDUZZHO/vZaLdGaMKfV1SXlBZw+rpoIUzkuLmLfG4I2BWsl 7pcguEaoOQkFtNxWSKFA2YY= X-Google-Smtp-Source: ABhQp+SDS1J9bUkI1t4gIu3/eEyRrWXpFxH8vtUDhATW1EdXbGKuOtJAenuvNYC9pfdsxb/Ihl9FPw== X-Received: by 10.101.69.197 with SMTP id m5mr358690pgr.200.1509415949784; Mon, 30 Oct 2017 19:12:29 -0700 (PDT) Received: from aurora.jms.id.au ([45.124.203.19]) by smtp.gmail.com with ESMTPSA id s87sm384404pfi.23.2017.10.30.19.12.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 30 Oct 2017 19:12:28 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 31 Oct 2017 12:42:19 +1030 From: Joel Stanley To: Jonathan Cameron , Rick Altherr , Rob Herring Cc: Philipp Zabel , Hartmut Knaack , Lars-Peter Clausen , Peter Meerwald-Stadler , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] iio: adc: aspeed: Deassert reset in probe Date: Tue, 31 Oct 2017 12:42:03 +1030 Message-Id: <20171031021203.18248-1-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 Sender: linux-iio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The ASPEED SoC must deassert a reset in order to use the ADC peripheral. The device tree bindings are updated to document the resets phandle, and the example is updated to match what is expected for both the reset and clock phandle. Note that the bindings should have always had the reset controller, as the hardware is unusable without it. Signed-off-by: Joel Stanley Reviewed-by: Philipp Zabel Acked-by: Rob Herring --- v2: - Ensure disabling path unwinds in opposite order as the enable path - Note that the bindings were incorrect without the reset phandle, and for the system to be usable we must update them. No one was (successfully) using these bindings/driver before without out of tree hacks in mach-aspeed, as it would not have worked. .../devicetree/bindings/iio/adc/aspeed_adc.txt | 4 +++- drivers/iio/adc/aspeed_adc.c | 25 ++++++++++++++++------ 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt index 674e133b7cd7..034fc2ba100e 100644 --- a/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt @@ -8,6 +8,7 @@ Required properties: - reg: memory window mapping address and length - clocks: Input clock used to derive the sample clock. Expected to be the SoC's APB clock. +- resets: Reset controller phandle - #io-channel-cells: Must be set to <1> to indicate channels are selected by index. @@ -15,6 +16,7 @@ Example: adc@1e6e9000 { compatible = "aspeed,ast2400-adc"; reg = <0x1e6e9000 0xb0>; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_ADC>; #io-channel-cells = <1>; }; diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 8a958d5f1905..327a49ba1991 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -53,11 +54,12 @@ struct aspeed_adc_model_data { }; struct aspeed_adc_data { - struct device *dev; - void __iomem *base; - spinlock_t clk_lock; - struct clk_hw *clk_prescaler; - struct clk_hw *clk_scaler; + struct device *dev; + void __iomem *base; + spinlock_t clk_lock; + struct clk_hw *clk_prescaler; + struct clk_hw *clk_scaler; + struct reset_control *rst; }; #define ASPEED_CHAN(_idx, _data_reg_addr) { \ @@ -217,6 +219,15 @@ static int aspeed_adc_probe(struct platform_device *pdev) goto scaler_error; } + data->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(data->rst)) { + dev_err(&pdev->dev, + "invalid or missing reset controller device tree entry"); + ret = PTR_ERR(data->rst); + goto reset_error; + } + reset_control_deassert(data->rst); + model_data = of_device_get_match_data(&pdev->dev); if (model_data->wait_init_sequence) { @@ -263,9 +274,10 @@ static int aspeed_adc_probe(struct platform_device *pdev) writel(ASPEED_OPERATION_MODE_POWER_DOWN, data->base + ASPEED_REG_ENGINE_CONTROL); clk_disable_unprepare(data->clk_scaler->clk); +reset_error: + reset_control_assert(data->rst); clk_enable_error: clk_hw_unregister_divider(data->clk_scaler); - scaler_error: clk_hw_unregister_divider(data->clk_prescaler); return ret; @@ -280,6 +292,7 @@ static int aspeed_adc_remove(struct platform_device *pdev) writel(ASPEED_OPERATION_MODE_POWER_DOWN, data->base + ASPEED_REG_ENGINE_CONTROL); clk_disable_unprepare(data->clk_scaler->clk); + reset_control_assert(data->rst); clk_hw_unregister_divider(data->clk_scaler); clk_hw_unregister_divider(data->clk_prescaler);