| Message ID | 20181103231024.659-2-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | meson-saradc: add chip temperature support | expand |
On Sun, 4 Nov 2018 00:10:23 +0100 Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > The 32-bit Meson8 SoC can use the SAR ADC to read the chip temperature. > This requires setting the correct TSC (temperature sensor coefficient), > which is programmed into the eFuse during the manufacturing process. > Meson8b and Meson8m2 are not supported yet because they have a 5-bit TSC > and only the first four bits are stored inside the SAR ADC registers. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> This 'seems' uncontroversial, but if I've missed something and the DT maintainers want to comment that is of course great! Applied to the togreg branch of iio.git and pushed out as testing for the autobuilders to play with it. Thanks, Jonathan > --- > .../devicetree/bindings/iio/adc/amlogic,meson-saradc.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt > index 54b823f3a453..325090e43ce6 100644 > --- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt > +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt > @@ -22,6 +22,12 @@ Required properties: > - vref-supply: the regulator supply for the ADC reference voltage > - #io-channel-cells: must be 1, see ../iio-bindings.txt > > +Optional properties: > +- nvmem-cells: phandle to the temperature_calib eFuse cells > +- nvmem-cell-names: if present (to enable the temperature sensor > + calibration) this must contain "temperature_calib" > + > + > Example: > saradc: adc@8680 { > compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
On Sun, 4 Nov 2018 00:10:23 +0100, Martin Blumenstingl wrote: > The 32-bit Meson8 SoC can use the SAR ADC to read the chip temperature. > This requires setting the correct TSC (temperature sensor coefficient), > which is programmed into the eFuse during the manufacturing process. > Meson8b and Meson8m2 are not supported yet because they have a 5-bit TSC > and only the first four bits are stored inside the SAR ADC registers. > > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- > .../devicetree/bindings/iio/adc/amlogic,meson-saradc.txt | 6 ++++++ > 1 file changed, 6 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt index 54b823f3a453..325090e43ce6 100644 --- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt @@ -22,6 +22,12 @@ Required properties: - vref-supply: the regulator supply for the ADC reference voltage - #io-channel-cells: must be 1, see ../iio-bindings.txt +Optional properties: +- nvmem-cells: phandle to the temperature_calib eFuse cells +- nvmem-cell-names: if present (to enable the temperature sensor + calibration) this must contain "temperature_calib" + + Example: saradc: adc@8680 { compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
The 32-bit Meson8 SoC can use the SAR ADC to read the chip temperature. This requires setting the correct TSC (temperature sensor coefficient), which is programmed into the eFuse during the manufacturing process. Meson8b and Meson8m2 are not supported yet because they have a 5-bit TSC and only the first four bits are stored inside the SAR ADC registers. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- .../devicetree/bindings/iio/adc/amlogic,meson-saradc.txt | 6 ++++++ 1 file changed, 6 insertions(+)