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Tue, 13 Aug 2019 07:55:48 +0000 Received: from NWD2HUBCAS7.ad.analog.com (nwd2hubcas7.ad.analog.com [10.64.69.107]) by nwd2mta1.analog.com (8.13.8/8.13.8) with ESMTP id x7D7tjmD015992 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=OK); Tue, 13 Aug 2019 00:55:45 -0700 Received: from mircea-Latitude-E6540.ad.analog.com (10.48.65.115) by NWD2HUBCAS7.ad.analog.com (10.64.69.107) with Microsoft SMTP Server id 14.3.408.0; Tue, 13 Aug 2019 03:55:48 -0400 From: Mircea Caprioru To: CC: , , , , , , , , Mircea Caprioru Subject: [PATCH V2 1/4] staging: iio: adc: ad7192: Add low_pass_3db_filter_frequency Date: Tue, 13 Aug 2019 10:55:41 +0300 Message-ID: <20190813075544.9122-1-mircea.caprioru@analog.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-ADIRoutedOnPrem: True X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:137.71.25.55;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(346002)(376002)(39860400002)(136003)(396003)(2980300002)(199004)(189003)(54534003)(2351001)(106002)(8676002)(246002)(6916009)(316002)(47776003)(4326008)(476003)(186003)(48376002)(2616005)(16586007)(7636002)(1076003)(26005)(305945005)(7696005)(86362001)(54906003)(51416003)(44832011)(478600001)(70586007)(36756003)(70206006)(14444005)(2906002)(336012)(426003)(126002)(5660300002)(50466002)(50226002)(107886003)(6666004)(356004)(8936002)(486006);DIR:OUT;SFP:1101;SCL:1;SRVR:DM5PR03MB2633;H:nwd2mta1.analog.com;FPR:;SPF:Pass;LANG:en;PTR:nwd2mail10.analog.com;A:1;MX:1; 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When setting the required cutoff frequency we also determine the ADC configuration for chop and sync filter. Signed-off-by: Mircea Caprioru --- Changelog V2: - no changes here drivers/staging/iio/adc/ad7192.c | 148 +++++++++++++++++++++++++++---- 1 file changed, 132 insertions(+), 16 deletions(-) diff --git a/drivers/staging/iio/adc/ad7192.c b/drivers/staging/iio/adc/ad7192.c index 81ea2639c67c..d58ce08f3693 100644 --- a/drivers/staging/iio/adc/ad7192.c +++ b/drivers/staging/iio/adc/ad7192.c @@ -143,6 +143,10 @@ #define AD7192_EXT_FREQ_MHZ_MAX 5120000 #define AD7192_INT_FREQ_MHZ 4915200 +#define AD7192_NO_SYNC_FILTER 1 +#define AD7192_SYNC3_FILTER 3 +#define AD7192_SYNC4_FILTER 4 + /* NOTE: * The AD7190/2/5 features a dual use data out ready DOUT/RDY output. * In order to avoid contentions on the SPI bus, it's therefore necessary @@ -250,7 +254,7 @@ static int ad7192_of_clock_select(struct ad7192_state *st) static int ad7192_setup(struct ad7192_state *st, struct device_node *np) { struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi); - bool rej60_en, sinc3_en, refin2_en, chop_en; + bool rej60_en, refin2_en; bool buf_en, bipolar, burnout_curr_en; unsigned long long scale_uv; int i, ret, id; @@ -282,24 +286,12 @@ static int ad7192_setup(struct ad7192_state *st, struct device_node *np) if (rej60_en) st->mode |= AD7192_MODE_REJ60; - sinc3_en = of_property_read_bool(np, "adi,sinc3-filter-enable"); - if (sinc3_en) - st->mode |= AD7192_MODE_SINC3; - refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable"); if (refin2_en && st->devid != ID_AD7195) st->conf |= AD7192_CONF_REFSEL; - chop_en = of_property_read_bool(np, "adi,chop-enable"); - if (chop_en) { - st->conf |= AD7192_CONF_CHOP; - if (sinc3_en) - st->f_order = 3; /* SINC 3rd order */ - else - st->f_order = 4; /* SINC 4th order */ - } else { - st->f_order = 1; - } + st->conf &= ~AD7192_CONF_CHOP; + st->f_order = AD7192_NO_SYNC_FILTER; buf_en = of_property_read_bool(np, "adi,buffer-enable"); if (buf_en) @@ -311,7 +303,7 @@ static int ad7192_setup(struct ad7192_state *st, struct device_node *np) burnout_curr_en = of_property_read_bool(np, "adi,burnout-currents-enable"); - if (burnout_curr_en && buf_en && !chop_en) { + if (burnout_curr_en && buf_en) { st->conf |= AD7192_CONF_BURN; } else if (burnout_curr_en) { dev_warn(&st->sd.spi->dev, @@ -409,6 +401,49 @@ static ssize_t ad7192_set(struct device *dev, return ret ? ret : len; } +static void ad7192_get_available_filter_freq(struct ad7192_state *st, + int *freq) +{ + unsigned int fadc; + + /* Formulas for filter at page 25 of the datasheet */ + fadc = DIV_ROUND_CLOSEST(st->fclk, + AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode)); + freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); + + fadc = DIV_ROUND_CLOSEST(st->fclk, + AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode)); + freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024); + + fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode)); + freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024); + freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024); +} + +static int ad7192_show_filter_avail(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct ad7192_state *st = iio_priv(indio_dev); + unsigned int freq_avail[4], i; + size_t len = 0; + + ad7192_get_available_filter_freq(st, freq_avail); + + for (i = 0; i < ARRAY_SIZE(freq_avail); i++) + len += scnprintf(buf + len, PAGE_SIZE - len, + "%d.%d ", freq_avail[i] / 1000, + freq_avail[i] % 1000); + + buf[len - 1] = '\n'; + + return len; +} + +static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available, + 0444, ad7192_show_filter_avail, NULL, 0); + static IIO_DEVICE_ATTR(bridge_switch_en, 0644, ad7192_show_bridge_switch, ad7192_set, AD7192_REG_GPOCON); @@ -418,6 +453,7 @@ static IIO_DEVICE_ATTR(ac_excitation_en, 0644, AD7192_REG_MODE); static struct attribute *ad7192_attributes[] = { + &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, &iio_dev_attr_bridge_switch_en.dev_attr.attr, &iio_dev_attr_ac_excitation_en.dev_attr.attr, NULL @@ -428,6 +464,7 @@ static const struct attribute_group ad7192_attribute_group = { }; static struct attribute *ad7195_attributes[] = { + &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, &iio_dev_attr_bridge_switch_en.dev_attr.attr, NULL }; @@ -441,6 +478,74 @@ static unsigned int ad7192_get_temp_scale(bool unipolar) return unipolar ? 2815 * 2 : 2815; } +static int ad7192_set_3db_filter_freq(struct ad7192_state *st, + int val, int val2) +{ + int freq_avail[4], i, ret, idx, freq; + unsigned int diff_new, diff_old; + + diff_old = U32_MAX; + freq = val * 1000 + val2; + + ad7192_get_available_filter_freq(st, freq_avail); + + for (i = 0; i < ARRAY_SIZE(freq_avail); i++) { + diff_new = abs(freq - freq_avail[i]); + if (diff_new < diff_old) { + diff_old = diff_new; + idx = i; + } + } + + switch (idx) { + case 0: + st->f_order = AD7192_SYNC4_FILTER; + st->mode &= ~AD7192_MODE_SINC3; + + st->conf |= AD7192_CONF_CHOP; + break; + case 1: + st->f_order = AD7192_SYNC3_FILTER; + st->mode |= AD7192_MODE_SINC3; + + st->conf |= AD7192_CONF_CHOP; + break; + case 2: + st->f_order = AD7192_NO_SYNC_FILTER; + st->mode &= ~AD7192_MODE_SINC3; + + st->conf &= ~AD7192_CONF_CHOP; + break; + case 3: + st->f_order = AD7192_NO_SYNC_FILTER; + st->mode |= AD7192_MODE_SINC3; + + st->conf &= ~AD7192_CONF_CHOP; + break; + } + + ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); + if (ret < 0) + return ret; + + return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); +} + +static int ad7192_get_3db_filter_freq(struct ad7192_state *st) +{ + unsigned int fadc; + + fadc = DIV_ROUND_CLOSEST(st->fclk, + st->f_order * AD7192_MODE_RATE(st->mode)); + + if (st->conf & AD7192_CONF_CHOP) + return DIV_ROUND_CLOSEST(fadc * 240, 1024); + if (st->mode & AD7192_MODE_SINC3) + return DIV_ROUND_CLOSEST(fadc * 272, 1024); + else + return DIV_ROUND_CLOSEST(fadc * 230, 1024); +} + static int ad7192_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, @@ -481,6 +586,10 @@ static int ad7192_read_raw(struct iio_dev *indio_dev, *val = st->fclk / (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)); return IIO_VAL_INT; + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + *val = ad7192_get_3db_filter_freq(st); + *val2 = 1000; + return IIO_VAL_FRACTIONAL; } return -EINVAL; @@ -535,6 +644,9 @@ static int ad7192_write_raw(struct iio_dev *indio_dev, st->mode |= AD7192_MODE_RATE(div); ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); break; + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000); + break; default: ret = -EINVAL; } @@ -553,6 +665,8 @@ static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev, return IIO_VAL_INT_PLUS_NANO; case IIO_CHAN_INFO_SAMP_FREQ: return IIO_VAL_INT; + case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: + return IIO_VAL_INT_PLUS_MICRO; default: return -EINVAL; } @@ -653,6 +767,8 @@ static int ad7192_channels_config(struct iio_dev *indio_dev) for (i = 0; i < indio_dev->num_channels; i++) { *chan = channels[i]; + chan->info_mask_shared_by_all |= + BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY); if (chan->type != IIO_TEMP) chan->info_mask_shared_by_type_available |= BIT(IIO_CHAN_INFO_SCALE);