[v2,3/4] clk: renesas: r9a07g044-cpg: Add clock and reset entries for ADC

Commit Message

Prabhakar July 19, 2021, 8:58 a.m. UTC

Add clock and reset entries for ADC block in CPG driver.

Signed-off-by: Lad Prabhakar <[e-mail]>
Reviewed-by: Biju Das <[e-mail]>
---
 drivers/clk/renesas/r9a07g044-cpg.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Geert Uytterhoeven July 19, 2021, 9:15 a.m. UTC | #1

On Mon, Jul 19, 2021 at 10:59 AM Lad Prabhakar
<[e-mail]> wrote:
> Add clock and reset entries for ADC block in CPG driver.
>
> Signed-off-by: Lad Prabhakar <[e-mail]>
> Reviewed-by: Biju Das <[e-mail]>

Reviewed-by: Geert Uytterhoeven <[e-mail]>
i.e. will queue in renesas-clk-for-v5.15.

Gr{oetje,eeting}s,

                        Geert

Patch

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index ae24e0397d3c..f4ebbde358c6 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -102,6 +102,10 @@  static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
 				0x584, 4),
 	DEF_MOD("sci0",		R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
 				0x588, 0),
+	DEF_MOD("adc_adclk",	R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU,
+				0x5a8, 0),
+	DEF_MOD("adc_pclk",	R9A07G044_ADC_PCLK, R9A07G044_CLK_P0,
+				0x5a8, 1),
 };
 
 static struct rzg2l_reset r9a07g044_resets[] = {
@@ -114,6 +118,8 @@  static struct rzg2l_reset r9a07g044_resets[] = {
 	DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
 	DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
 	DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
+	DEF_RST(R9A07G044_ADC_PRESETN, 0x8a8, 0),
+	DEF_RST(R9A07G044_ADC_ADRST_N, 0x8a8, 1),
 };
 
 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {