From patchwork Fri Oct 15 08:14:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 12560443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84500C4332F for ; Fri, 15 Oct 2021 08:15:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6CEBF6108B for ; Fri, 15 Oct 2021 08:15:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236773AbhJOIRr (ORCPT ); Fri, 15 Oct 2021 04:17:47 -0400 Received: from relay7-d.mail.gandi.net ([217.70.183.200]:51139 "EHLO relay7-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236775AbhJOIRd (ORCPT ); Fri, 15 Oct 2021 04:17:33 -0400 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay7-d.mail.gandi.net (Postfix) with ESMTPSA id 284C420013; Fri, 15 Oct 2021 08:15:25 +0000 (UTC) From: Miquel Raynal To: Jonathan Cameron , Lee Jones , linux-iio@vger.kernel.org, linux-omap@vger.kernel.org, Thomas Petazzoni , Ryan Barnett , linux-kernel@vger.kernel.org Cc: Miquel Raynal , Jonathan Cameron Subject: [PATCH v6 13/48] mfd: ti_am335x_tscadc: Reword the comment explaining the dividers Date: Fri, 15 Oct 2021 10:14:31 +0200 Message-Id: <20211015081506.933180-14-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211015081506.933180-1-miquel.raynal@bootlin.com> References: <20211015081506.933180-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org The comment misses the main information which is that we assume that a sample takes 15 ADC clock cycles to be generated. Let's take the occasion to rework a little bit this comment. Signed-off-by: Miquel Raynal Reviewed-by: Jonathan Cameron --- drivers/mfd/ti_am335x_tscadc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/mfd/ti_am335x_tscadc.c b/drivers/mfd/ti_am335x_tscadc.c index e090fed89c6f..e2c4416f192d 100644 --- a/drivers/mfd/ti_am335x_tscadc.c +++ b/drivers/mfd/ti_am335x_tscadc.c @@ -199,12 +199,12 @@ static int ti_tscadc_probe(struct platform_device *pdev) pm_runtime_get_sync(&pdev->dev); /* - * The TSC_ADC_Subsystem has 2 clock domains - * OCP_CLK and ADC_CLK. - * The ADC clock is expected to run at target of 3MHz, - * and expected to capture 12-bit data at a rate of 200 KSPS. - * The TSC_ADC_SS controller design assumes the OCP clock is - * at least 6x faster than the ADC clock. + * The TSC_ADC_Subsystem has 2 clock domains: OCP_CLK and ADC_CLK. + * ADCs produce a 12-bit sample every 15 ADC_CLK cycles. + * am33xx ADCs expect to capture 200ksps. + * We need the ADC clocks to run at 3MHz. + * This frequency is valid since TSC_ADC_SS controller design + * assumes the OCP clock is at least 6x faster than the ADC clock. */ clk = devm_clk_get(&pdev->dev, "adc_tsc_fck"); if (IS_ERR(clk)) {