From patchwork Wed Nov 17 08:46:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gwendal Grignou X-Patchwork-Id: 12623937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0452BC433FE for ; Wed, 17 Nov 2021 08:46:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DF9FB61548 for ; Wed, 17 Nov 2021 08:46:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233823AbhKQIto (ORCPT ); Wed, 17 Nov 2021 03:49:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233830AbhKQItk (ORCPT ); Wed, 17 Nov 2021 03:49:40 -0500 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B3B5C061764 for ; Wed, 17 Nov 2021 00:46:42 -0800 (PST) Received: by mail-pj1-x102b.google.com with SMTP id x7so1832661pjn.0 for ; Wed, 17 Nov 2021 00:46:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MTLglvmO1QPHilN5tr9eBj6bVQJYdzGPS4mWPbSZm7w=; b=LoiUbNyJtTcfs659C5FqW8dCZENCFmDuPr8gvuq8cbj7RDHCqRODqVhzaZYs++N+2l Iorl70s3WoDN9hzZaEYeq8+gbrfeZda7EBDVlX6l3CXFqHk+zoOtA9L8UuTcysMkD1Ae u5fQGjInxjYr8aC/Txcw9eGfoXapRuLadtmco= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MTLglvmO1QPHilN5tr9eBj6bVQJYdzGPS4mWPbSZm7w=; b=wKBx3f8DK1dSJ702s5oi0q7rCKcWXEyAqbEEFPho8PZTxAC3CC17JQ1PNmrQTMJGYp KIruFj79n5+sNodIhbXrf/kdd1F32slGdPVNerItttkcCjf5+BFQorDIc0yTMccLUN8L cpvHoA4/hOwcmRubjjRFWfOLBqVpe5wjHNWBMJAZq+v6/7hVnj8eNY8qSqgwW0xsynl/ 8hNEowwd1ynBlSWGQEBgACjeyWWSIyMGjjpYE5kKzIRlzmM/P+JzijSgTp3seFNJFJqY puIg2MO1U8oT+swVuP+W/TwV7VGbndNb1IbIrZz/eYWgAX6PqWi+A4nhi5dtyB8Lza96 mavg== X-Gm-Message-State: AOAM533Jpngw5RUhdqmp8HhOIZGTN9lBxitkq+xk7u1NgB8tsmeLHwZE GDBnc5zMK5WlklrekdsyMq0TckKBoy5NAA== X-Google-Smtp-Source: ABdhPJxMogWwkRkFAaqjyDUf41P/k1RNd3RvZrDoHXmZzXpMrideJvj9B4GQLkX9UK7VubGGcMDFfQ== X-Received: by 2002:a17:903:32d1:b0:142:1ce1:30c9 with SMTP id i17-20020a17090332d100b001421ce130c9mr52633830plr.0.1637138801791; Wed, 17 Nov 2021 00:46:41 -0800 (PST) Received: from localhost ([2620:15c:202:201:327f:7baa:380e:33a3]) by smtp.gmail.com with UTF8SMTPSA id u23sm4726124pfl.105.2021.11.17.00.46.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Nov 2021 00:46:41 -0800 (PST) From: Gwendal Grignou To: jic23@kernel.org, lars@metafoo.de, swboyd@chromium.org Cc: andy.shevchenko@gmail.com, linux-iio@vger.kernel.org, Gwendal Grignou Subject: [PATCH v3 5/5] iio: sx9324: Add dt_bidding support Date: Wed, 17 Nov 2021 00:46:31 -0800 Message-Id: <20211117084631.2820014-6-gwendal@chromium.org> X-Mailer: git-send-email 2.34.0.rc1.387.gb447b232ab-goog In-Reply-To: <20211117084631.2820014-1-gwendal@chromium.org> References: <20211117084631.2820014-1-gwendal@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Based on bindings/iio/proximity/semtech,sx9324.yaml, implement retrieving sensor hardware property and alter default values. Signed-off-by: Gwendal Grignou --- Changes in v3: - Fix constant names. - Remove "avg-neg-strength" binding support. - Add "semtech,proxraw-strengthXX" binding support. - Simplify processing of bindings when a register is set by one binding only: in case of failure, just break with the default value. - Fix a calculation error from binding to register. Changes in v2: - Use new interface. drivers/iio/proximity/sx9324.c | 158 +++++++++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/drivers/iio/proximity/sx9324.c b/drivers/iio/proximity/sx9324.c index 21423999a192ff..074a54c0280941 100644 --- a/drivers/iio/proximity/sx9324.c +++ b/drivers/iio/proximity/sx9324.c @@ -85,6 +85,7 @@ #define SX9324_REG_PROX_CTRL0 0x30 #define SX9324_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3) #define SX9324_REG_PROX_CTRL0_GAIN_1 0x80 +#define SX9324_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0) #define SX9324_REG_PROX_CTRL0_RAWFILT_1P50 0x01 #define SX9324_REG_PROX_CTRL1 0x31 #define SX9324_REG_PROX_CTRL2 0x32 @@ -756,6 +757,74 @@ static int sx9324_write_raw(struct iio_dev *indio_dev, return -EINVAL; } +static const struct sx_common_reg_default sx9324_default_regs[] = { + { SX9324_REG_IRQ_MSK, 0x00 }, + { SX9324_REG_IRQ_CFG0, 0x00 }, + { SX9324_REG_IRQ_CFG1, SX9324_REG_IRQ_CFG1_FAILCOND }, + { SX9324_REG_IRQ_CFG2, 0x00 }, + { SX9324_REG_GNRL_CTRL0, SX9324_REG_GNRL_CTRL0_SCANPERIOD_100MS }, + /* + * The lower 4 bits should not be set as it enable sensors measurements. + * Turning the detection on before the configuration values are set to + * good values can cause the device to return erroneous readings. + */ + { SX9324_REG_GNRL_CTRL1, SX9324_REG_GNRL_CTRL1_PAUSECTRL }, + + { SX9324_REG_AFE_CTRL0, 0x00 }, + { SX9324_REG_AFE_CTRL3, 0x00 }, + { SX9324_REG_AFE_CTRL4, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ | + SX9324_REG_AFE_CTRL4_RES_100 }, + { SX9324_REG_AFE_CTRL6, 0x00 }, + { SX9324_REG_AFE_CTRL7, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ | + SX9324_REG_AFE_CTRL4_RES_100 }, + + /* TODO(gwendal): PHx use chip default or all grounded? */ + { SX9324_REG_AFE_PH0, 0x29 }, + { SX9324_REG_AFE_PH1, 0x26 }, + { SX9324_REG_AFE_PH2, 0x1a }, + { SX9324_REG_AFE_PH3, 0x16 }, + + { SX9324_REG_AFE_CTRL8, SX9324_REG_AFE_CTRL8_RESFILTN_4KOHM }, + { SX9324_REG_AFE_CTRL9, SX9324_REG_AFE_CTRL9_AGAIN_1 }, + + { SX9324_REG_PROX_CTRL0, SX9324_REG_PROX_CTRL0_GAIN_1 | + SX9324_REG_PROX_CTRL0_RAWFILT_1P50 }, + { SX9324_REG_PROX_CTRL1, SX9324_REG_PROX_CTRL0_GAIN_1 | + SX9324_REG_PROX_CTRL0_RAWFILT_1P50 }, + { SX9324_REG_PROX_CTRL2, SX9324_REG_PROX_CTRL2_AVGNEG_THRESH_16K }, + { SX9324_REG_PROX_CTRL3, SX9324_REG_PROX_CTRL3_AVGDEB_2SAMPLES | + SX9324_REG_PROX_CTRL3_AVGPOS_THRESH_16K }, + { SX9324_REG_PROX_CTRL4, SX9324_REG_PROX_CTRL4_AVGNEG_FILT_2 | + SX9324_REG_PROX_CTRL3_AVGPOS_FILT_256 }, + { SX9324_REG_PROX_CTRL5, 0x00 }, + { SX9324_REG_PROX_CTRL6, SX9324_REG_PROX_CTRL6_PROXTHRESH_32 }, + { SX9324_REG_PROX_CTRL7, SX9324_REG_PROX_CTRL6_PROXTHRESH_32 }, + { SX9324_REG_ADV_CTRL0, 0x00 }, + { SX9324_REG_ADV_CTRL1, 0x00 }, + { SX9324_REG_ADV_CTRL2, 0x00 }, + { SX9324_REG_ADV_CTRL3, 0x00 }, + { SX9324_REG_ADV_CTRL4, 0x00 }, + { SX9324_REG_ADV_CTRL5, SX9324_REG_ADV_CTRL5_STARTUP_SENSOR_1 | + SX9324_REG_ADV_CTRL5_STARTUP_METHOD_1 }, + { SX9324_REG_ADV_CTRL6, 0x00 }, + { SX9324_REG_ADV_CTRL7, 0x00 }, + { SX9324_REG_ADV_CTRL8, 0x00 }, + { SX9324_REG_ADV_CTRL9, 0x00 }, + /* Body/Table threshold */ + { SX9324_REG_ADV_CTRL10, 0x00 }, + { SX9324_REG_ADV_CTRL11, 0x00 }, + { SX9324_REG_ADV_CTRL12, 0x00 }, + /* TODO(gwendal): SAR currenly disabled */ + { SX9324_REG_ADV_CTRL13, 0x00 }, + { SX9324_REG_ADV_CTRL14, 0x00 }, + { SX9324_REG_ADV_CTRL15, 0x00 }, + { SX9324_REG_ADV_CTRL16, 0x00 }, + { SX9324_REG_ADV_CTRL17, 0x00 }, + { SX9324_REG_ADV_CTRL18, 0x00 }, + { SX9324_REG_ADV_CTRL19, SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION }, + { SX9324_REG_ADV_CTRL20, SX9324_REG_ADV_CTRL19_HIGHT_FAILURE_THRESH_SATURATION }, +}; + /* Activate all channels and perform an initial compensation. */ static int sx9324_init_compensation(struct iio_dev *indio_dev) { @@ -780,6 +849,93 @@ static int sx9324_init_compensation(struct iio_dev *indio_dev) return ret; } +static const struct sx_common_reg_default * +sx9324_get_default_reg(struct device *dev, int idx, + struct sx_common_reg_default *reg_def) +{ +#define SX9324_PIN_DEF "semtech,ph0-pin" +#define SX9324_RESOLUTION_DEF "semtech,resolution01" +#define SX9324_PROXRAW_DEF "semtech,proxraw-strength01" + unsigned int pin_defs[SX9324_NUM_PINS]; + char prop[] = SX9324_PROXRAW_DEF; + u32 start = 0, raw = 0, pos = 0; + int ret, count, ph, pin; + + memcpy(reg_def, &sx9324_default_regs[idx], sizeof(*reg_def)); + switch (reg_def->reg) { + case SX9324_REG_AFE_PH0: + case SX9324_REG_AFE_PH1: + case SX9324_REG_AFE_PH2: + case SX9324_REG_AFE_PH3: + ph = reg_def->reg - SX9324_REG_AFE_PH0; + scnprintf(prop, ARRAY_SIZE(prop), "semtech,ph%d-pin", ph); + + count = device_property_count_u32(dev, prop); + if (count != ARRAY_SIZE(pin_defs)) + break; + ret = device_property_read_u32_array(dev, prop, pin_defs, + ARRAY_SIZE(pin_defs)); + for (pin = 0; pin < SX9324_NUM_PINS; pin++) + raw |= (pin_defs[pin] << (2 * pin)) & + SX9324_REG_AFE_PH0_PIN_MASK(pin); + reg_def->def = raw; + break; + case SX9324_REG_AFE_CTRL4: + case SX9324_REG_AFE_CTRL7: + if (reg_def->reg == SX9324_REG_AFE_CTRL4) + strncpy(prop, "semtech,resolution01", ARRAY_SIZE(prop)); + else + strncpy(prop, "semtech,resolution23", ARRAY_SIZE(prop)); + + ret = device_property_read_u32(dev, prop, &raw); + if (ret) + break; + + raw = ilog2(raw) - 3; + + reg_def->def &= ~SX9324_REG_AFE_CTRL4_RESOLUTION_MASK; + reg_def->def |= FIELD_PREP(SX9324_REG_AFE_CTRL4_RESOLUTION_MASK, + raw); + break; + case SX9324_REG_ADV_CTRL5: + ret = device_property_read_u32(dev, "semtech,startup-sensor", &start); + if (ret) + break; + + reg_def->def &= ~SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK; + reg_def->def |= FIELD_PREP(SX9324_REG_ADV_CTRL5_STARTUPSENS_MASK, + start); + break; + case SX9324_REG_PROX_CTRL4: + ret = device_property_read_u32(dev, "semtech,avg-pos-strength", &pos); + if (ret) + break; + + /* Powers of 2, except for a gap between 16 and 64 */ + raw = clamp(ilog2(pos), 3, 11) - (pos >= 32 ? 4 : 3); + + reg_def->def &= ~SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK; + reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL4_AVGPOSFILT_MASK, + raw); + break; + case SX9324_REG_PROX_CTRL0: + case SX9324_REG_PROX_CTRL1: + if (reg_def->reg == SX9324_REG_PROX_CTRL0) + strncpy(prop, "semtech,proxraw-strength01", ARRAY_SIZE(prop)); + else + strncpy(prop, "semtech,proxraw-strength23", ARRAY_SIZE(prop)); + ret = device_property_read_u32(dev, prop, &raw); + if (ret) + break; + + reg_def->def &= ~SX9324_REG_PROX_CTRL0_RAWFILT_MASK; + reg_def->def |= FIELD_PREP(SX9324_REG_PROX_CTRL0_RAWFILT_MASK, + raw); + break; + } + return reg_def; +} + static int sx9324_check_whoami(struct device *dev, struct iio_dev *indio_dev) { @@ -821,12 +977,14 @@ static const struct sx_common_chip_info sx9324_chip_info = { .mask_enable_chan = SX9324_REG_GNRL_CTRL1_PHEN_MASK, .irq_msk_offset = 3, .num_channels = SX9324_NUM_CHANNELS, + .num_default_regs = ARRAY_SIZE(sx9324_default_regs), .ops = { .read_prox_data = sx9324_read_prox_data, .check_whoami = sx9324_check_whoami, .init_compensation = sx9324_init_compensation, .wait_for_sample = sx9324_wait_for_sample, + .get_default_reg = sx9324_get_default_reg, }, .iio_channels = sx9324_channels,