From patchwork Mon Dec 13 02:40:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gwendal Grignou X-Patchwork-Id: 12673023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6E63C43217 for ; Mon, 13 Dec 2021 02:41:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231341AbhLMClH (ORCPT ); Sun, 12 Dec 2021 21:41:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231328AbhLMClH (ORCPT ); Sun, 12 Dec 2021 21:41:07 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E39DC06173F for ; Sun, 12 Dec 2021 18:41:07 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id k6-20020a17090a7f0600b001ad9d73b20bso12147865pjl.3 for ; Sun, 12 Dec 2021 18:41:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H5kwivVF3x7ca3oQCkUe5KZchN/2sBJHEUtGxc/G+rk=; b=RcvhX9GoM27q4Oq2GIDR6A3XXy4xBBIjWjLE1iOqUSATktPWKCOWlrNReJAcIAEzB5 NR2Tbu7Qh4j1q7bSQ6ASy6ZU2rkbrhgWAaHEOiMF0wA0KM4Q0Rru81KRT7Y30bHjfXHj pcKzAyzr2VC9zfNqIBqq66m1XZdKBjcmQ0xW8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H5kwivVF3x7ca3oQCkUe5KZchN/2sBJHEUtGxc/G+rk=; b=EE14pLRHWzn1WQeaqOxXfjAHkQK+IJk3O4Y9sk4OsIkkUan+diN9/qIEo55ll7w14S 5CluO8FKpxY4elVYoLl6vl26Ht/MSOj2LEo1bfG6rAyz4zhFIxDj6FFAB8sf5+Dy6JhW w1unPxTEz2ph2oQapAQgo/e3sMJNrYtyF92jckGxzJKrX5kEX1uNsbCb0yyjNgx2pNv+ ZLiZ+VvDp8LczoIJgaVMJmvfk/UFxqE7aTsdFJMeOlP51kP9L9LlmPi9L5pYPDAV8n/R vK7QAlpYaJny3qazApCMh3qckf+NKjOr9Orbi9khJcvoW/6cISYydyIbAwVFSTTCQoO8 F5TA== X-Gm-Message-State: AOAM530Lloka8F9IGH14E0Ktc7h18e/MVugMD3aDZmg3fRetRu0+h9b/ tqlQjkgpjgKAe5d6lNmJYNmEHw== X-Google-Smtp-Source: ABdhPJxgVBxndwNfpeKY0YYyPfsJbj+fK4usMGIjhHEKrlU/oxB+sQCw/Z/ZD+V/iQMhyto5K8bpYw== X-Received: by 2002:a17:90a:c08a:: with SMTP id o10mr41492475pjs.44.1639363266616; Sun, 12 Dec 2021 18:41:06 -0800 (PST) Received: from localhost ([2620:15c:202:201:9cf8:7f4:ed82:2d07]) by smtp.gmail.com with UTF8SMTPSA id h15sm10802132pfc.134.2021.12.12.18.41.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 12 Dec 2021 18:41:06 -0800 (PST) From: Gwendal Grignou To: robh+dt@kernel.org, jic23@kernel.org, lars@metafoo.de, swboyd@chromium.org Cc: andy.shevchenko@gmail.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Gwendal Grignou Subject: [PATCH v3 4/4] iio: sx9360: Add dt-binding support Date: Sun, 12 Dec 2021 18:40:57 -0800 Message-Id: <20211213024057.3824985-5-gwendal@chromium.org> X-Mailer: git-send-email 2.34.1.173.g76aa8bc2d0-goog In-Reply-To: <20211213024057.3824985-1-gwendal@chromium.org> References: <20211213024057.3824985-1-gwendal@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org Add support to configure sx9360 from dt-binding, to match device hardware setup. Signed-off-by: Gwendal Grignou Reviewed-by: Stephen Boyd --- Changes since v2: - Add include when needed. - Move default register constant to main patch. No changes in v2. drivers/iio/proximity/sx9360.c | 85 +++++++++++++++++++++++++++++++++- 1 file changed, 84 insertions(+), 1 deletion(-) diff --git a/drivers/iio/proximity/sx9360.c b/drivers/iio/proximity/sx9360.c index aebfbe541e0e04..30cc6549d301e6 100644 --- a/drivers/iio/proximity/sx9360.c +++ b/drivers/iio/proximity/sx9360.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -64,6 +65,7 @@ #define SX9360_REG_PROX_CTRL0_PHM 0x41 #define SX9360_REG_PROX_CTRL0_GAIN_MASK GENMASK(5, 3) #define SX9360_REG_PROX_CTRL0_GAIN_1 0x80 +#define SX9360_REG_PROX_CTRL0_RAWFILT_MASK GENMASK(2, 0) #define SX9360_REG_PROX_CTRL0_RAWFILT_1P50 0x01 #define SX9360_REG_PROX_CTRL1 0x42 #define SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_MASK GENMASK(5, 3) @@ -647,6 +649,41 @@ static int sx9360_write_raw(struct iio_dev *indio_dev, return -EINVAL; } +static const struct sx_common_reg_default sx9360_default_regs[] = { + { SX9360_REG_IRQ_MSK, 0x00 }, + { SX9360_REG_IRQ_CFG, 0x00 }, + /* + * The lower 2 bits should not be set as it enable sensors measurements. + * Turning the detection on before the configuration values are set to + * good values can cause the device to return erroneous readings. + */ + { SX9360_REG_GNRL_CTRL0, 0x00 }, + { SX9360_REG_GNRL_CTRL1, 0x00 }, + { SX9360_REG_GNRL_CTRL2, SX9360_REG_GNRL_CTRL2_PERIOD_102MS }, + + { SX9360_REG_AFE_CTRL1, 0x00 }, + { SX9360_REG_AFE_PARAM0_PHR, SX9360_REG_AFE_PARAM0_RSVD | + SX9360_REG_AFE_PARAM0_RESOLUTION_128 }, + { SX9360_REG_AFE_PARAM1_PHR, SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF | + SX9360_REG_AFE_PARAM1_FREQ_83_33HZ }, + { SX9360_REG_AFE_PARAM0_PHM, SX9360_REG_AFE_PARAM0_RSVD | + SX9360_REG_AFE_PARAM0_RESOLUTION_128 }, + { SX9360_REG_AFE_PARAM1_PHM, SX9360_REG_AFE_PARAM1_AGAIN_PHM_6PF | + SX9360_REG_AFE_PARAM1_FREQ_83_33HZ }, + + { SX9360_REG_PROX_CTRL0_PHR, SX9360_REG_PROX_CTRL0_GAIN_1 | + SX9360_REG_PROX_CTRL0_RAWFILT_1P50 }, + { SX9360_REG_PROX_CTRL0_PHM, SX9360_REG_PROX_CTRL0_GAIN_1 | + SX9360_REG_PROX_CTRL0_RAWFILT_1P50 }, + { SX9360_REG_PROX_CTRL1, SX9360_REG_PROX_CTRL1_AVGNEG_THRESH_16K }, + { SX9360_REG_PROX_CTRL2, SX9360_REG_PROX_CTRL2_AVGDEB_2SAMPLES | + SX9360_REG_PROX_CTRL2_AVGPOS_THRESH_16K }, + { SX9360_REG_PROX_CTRL3, SX9360_REG_PROX_CTRL3_AVGNEG_FILT_2 | + SX9360_REG_PROX_CTRL3_AVGPOS_FILT_256 }, + { SX9360_REG_PROX_CTRL4, 0x00 }, + { SX9360_REG_PROX_CTRL5, SX9360_REG_PROX_CTRL5_PROXTHRESH_32 }, +}; + /* Activate all channels and perform an initial compensation. */ static int sx9360_init_compensation(struct iio_dev *indio_dev) { @@ -671,6 +708,51 @@ static int sx9360_init_compensation(struct iio_dev *indio_dev) return ret; } +static const struct sx_common_reg_default * +sx9360_get_default_reg(struct device *dev, int idx, + struct sx_common_reg_default *reg_def) +{ + u32 raw = 0, pos = 0; + int ret; + + memcpy(reg_def, &sx9360_default_regs[idx], sizeof(*reg_def)); + switch (reg_def->reg) { + case SX9360_REG_AFE_PARAM0_PHR: + case SX9360_REG_AFE_PARAM0_PHM: + ret = device_property_read_u32(dev, "semtech,resolution", &raw); + if (ret) + break; + + raw = ilog2(raw) - 3; + + reg_def->def &= ~SX9360_REG_AFE_PARAM0_RESOLUTION_MASK; + reg_def->def |= FIELD_PREP(SX9360_REG_AFE_PARAM0_RESOLUTION_MASK, raw); + break; + case SX9360_REG_PROX_CTRL0_PHR: + case SX9360_REG_PROX_CTRL0_PHM: + ret = device_property_read_u32(dev, "semtech,proxraw-strength", &raw); + if (ret) + break; + + reg_def->def &= ~SX9360_REG_PROX_CTRL0_RAWFILT_MASK; + reg_def->def |= FIELD_PREP(SX9360_REG_PROX_CTRL0_RAWFILT_MASK, raw); + break; + case SX9360_REG_PROX_CTRL3: + ret = device_property_read_u32(dev, "semtech,avg-pos-strength", + &pos); + if (ret) + break; + + /* Powers of 2, except for a gap between 16 and 64 */ + raw = clamp(ilog2(pos), 3, 11) - (pos >= 32 ? 4 : 3); + reg_def->def &= ~SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK; + reg_def->def |= FIELD_PREP(SX9360_REG_PROX_CTRL3_AVGPOS_FILT_MASK, raw); + break; + } + + return reg_def; +} + static int sx9360_check_whoami(struct device *dev, struct iio_dev *indio_dev) { @@ -691,12 +773,14 @@ static const struct sx_common_chip_info sx9360_chip_info = { .mask_enable_chan = SX9360_REG_GNRL_CTRL0_PHEN_MASK, .stat_offset = 3, .num_channels = SX9360_NUM_CHANNELS, + .num_default_regs = ARRAY_SIZE(sx9360_default_regs), .ops = { .read_prox_data = sx9360_read_prox_data, .check_whoami = sx9360_check_whoami, .init_compensation = sx9360_init_compensation, .wait_for_sample = sx9360_wait_for_sample, + .get_default_reg = sx9360_get_default_reg, }, .iio_channels = sx9360_channels,