| Message ID | 20220318162722.51215-7-alexandru.tachici@analog.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | iio: adc: ad_sigma_delta: Add sequencer support | expand |
On Fri, 18 Mar 2022 18:27:20 +0200 <alexandru.tachici@analog.com> wrote: > From: Alexandru Tachici <alexandru.tachici@analog.com> > > Add sequencer support for AD7192. > > Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com> > --- > drivers/iio/adc/ad7192.c | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c > index adff6472e075..e59753c61274 100644 > --- a/drivers/iio/adc/ad7192.c > +++ b/drivers/iio/adc/ad7192.c > @@ -58,7 +58,8 @@ > /* Mode Register Bit Designations (AD7192_REG_MODE) */ > #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */ > #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */ > -#define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */ > +#define AD7192_MODE_STA(x) (((x) & 0x1) << 20) /* Status Register transmission */ > +#define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */ > #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */ > #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */ > #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/ > @@ -288,12 +289,25 @@ static int ad7192_set_mode(struct ad_sigma_delta *sd, > return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); > } > > +static int ad7192_append_status(struct ad_sigma_delta *sd, bool append) > +{ > + struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); > + > + st->mode &= ~AD7192_MODE_STA_MASK; > + st->mode |= AD7192_MODE_STA(append); > + Another case where I would prefer the state cache be updated after the write succeeds unless there is some reason that doesn't make sense. + Swash patch 8 into this one so we don't leave a broken driver inbetween. Thanks, Jonathan > + return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); > +} > + > static const struct ad_sigma_delta_info ad7192_sigma_delta_info = { > .set_channel = ad7192_set_channel, > + .append_status = ad7192_append_status, > .set_mode = ad7192_set_mode, > .has_registers = true, > .addr_shift = 3, > .read_mask = BIT(6), > + .status_ch_mask = GENMASK(3, 0), > + .num_slots = 4, > .irq_flags = IRQF_TRIGGER_FALLING, > }; >
diff --git a/drivers/iio/adc/ad7192.c b/drivers/iio/adc/ad7192.c index adff6472e075..e59753c61274 100644 --- a/drivers/iio/adc/ad7192.c +++ b/drivers/iio/adc/ad7192.c @@ -58,7 +58,8 @@ /* Mode Register Bit Designations (AD7192_REG_MODE) */ #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */ #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */ -#define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */ +#define AD7192_MODE_STA(x) (((x) & 0x1) << 20) /* Status Register transmission */ +#define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */ #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */ #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */ #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/ @@ -288,12 +289,25 @@ static int ad7192_set_mode(struct ad_sigma_delta *sd, return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); } +static int ad7192_append_status(struct ad_sigma_delta *sd, bool append) +{ + struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); + + st->mode &= ~AD7192_MODE_STA_MASK; + st->mode |= AD7192_MODE_STA(append); + + return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); +} + static const struct ad_sigma_delta_info ad7192_sigma_delta_info = { .set_channel = ad7192_set_channel, + .append_status = ad7192_append_status, .set_mode = ad7192_set_mode, .has_registers = true, .addr_shift = 3, .read_mask = BIT(6), + .status_ch_mask = GENMASK(3, 0), + .num_slots = 4, .irq_flags = IRQF_TRIGGER_FALLING, };