From patchwork Tue May 3 08:58:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Cameron X-Patchwork-Id: 12835300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E383CC433F5 for ; Tue, 3 May 2022 08:51:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232984AbiECIz2 (ORCPT ); Tue, 3 May 2022 04:55:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230464AbiECIz1 (ORCPT ); Tue, 3 May 2022 04:55:27 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D1A921817 for ; Tue, 3 May 2022 01:51:55 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B46276128D for ; Tue, 3 May 2022 08:51:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5F185C385B1; Tue, 3 May 2022 08:51:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651567914; bh=h9r3d73XPxk1oBrIlOcP2R/gKealCiOCT99s4IAnug8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FGSH71V2F/Ojvca6Mqn9fsuzqBNse1L38CnWZ4/LOYjLPqCWnDNO0PBIpH7udadpa nLmfo7XfoKfG99ooamnA013ovSrJR+Y9t3RplahO3IegR+jzPVUnmK6Nji1UcJlXQp BO2wQLrllx54q4zlh6V+jolAwWkGPBfEtJ3WftKLO+hfRuSOZ85t+V2hnbOe98y97G BsRVi13H2w4ZY4WyS5F+g3FAIGVeE/R78qN8qBiTOxi+gVfoqSFuku+ghoN/epxiuP 5uPNcrlPeUREeF2Iimc2i8aS+wKWWQZwRXELjOw9JBQ16PyCc6VZUTor5YEMi7nuW2 57+ZYv3hUi55Q== From: Jonathan Cameron To: linux-iio@vger.kernel.org Cc: Akinobu Mita , Alexandru Lazar , Alexandru Tachici , Antoniu Miclaus , Charles-Antoine Couret , Cosmin Tanislav , Cristian Pop , David Lechner , Ivan Mikhaylov , Jacopo Mondi , Jean-Baptiste Maneyrol , Lars-Peter Clausen , Marcelo Schmitt , =?utf-8?q?M=C3=A5rten_Lindahl?= , Matt Ranostay , Michael Hennerich , Michael Welling , Mugilraj Dhavachelvan , Navin Sankar Velliangiri , =?utf-8?q?Nuno_S=C3=A1?= , Paul Cercueil , Phil Reid , Puranjay Mohan , Ricardo Ribalda , Robert Jones , Rui Miguel Silva , Sean Nyekjaer , Tomas Melin , Tomislav Denis , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Cameron Subject: [PATCH 01/92] iio: core: Fix IIO_ALIGN as it was not sufficiently large on some platforms. Date: Tue, 3 May 2022 09:58:04 +0100 Message-Id: <20220503085935.1533814-2-jic23@kernel.org> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220503085935.1533814-1-jic23@kernel.org> References: <20220503085935.1533814-1-jic23@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Jonathan Cameron Discussion of the series: https://lore.kernel.org/all/20220405135758.774016-1-catalin.marinas@arm.com/ mm, arm64: Reduce ARCH_KMALLOC_MINALIGN brought to my attention that our current IIO usage of L1CACHE_ALIGN is insufficient as their are Arm platforms out their with non coherent DMA and larger cache lines at at higher levels of their cache hierarchy. Note this patch will greatly reduce the padding on some architectures that have smaller requirements for DMA safe buffers. The history of changing values of ARCH_KMALLOC_MINALIGN via ARCH_DMA_MINALIGN on arm64 is rather complex. I'm not tagging this as fixing a particular patch from that route as it's not clear what to tag. Most recently a change to bring them back inline was reverted because of some Qualcomm Kryo cores with an L2 cache with 128-byte lines sitting above the point of coherency. c1132702c71f Revert "arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)" That reverts: 65688d2a05de arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) which refers to the change originally being motivated by Thunder x1 performance rather than correctness. Fixes: 6f7c8ee585e9d ("staging:iio: Add ability to allocate private data space to iio_allocate_device") Signed-off-by: Jonathan Cameron --- include/linux/iio/iio.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h index faf00f2c0be6..30937f8f9424 100644 --- a/include/linux/iio/iio.h +++ b/include/linux/iio/iio.h @@ -9,6 +9,7 @@ #include #include +#include #include #include /* IIO TODO LIST */ @@ -657,8 +658,13 @@ static inline void *iio_device_get_drvdata(const struct iio_dev *indio_dev) return dev_get_drvdata(&indio_dev->dev); } -/* Can we make this smaller? */ -#define IIO_ALIGN L1_CACHE_BYTES +/* + * Used to ensure the iio_priv() structure is aligned to allow that structure + * to in turn include IIO_ALIGN'd elements such as buffers which must not share + * cachelines with the rest of the structure, thus making them safe for use with + * non-coherent DMA. + */ +#define IIO_ALIGN ARCH_KMALLOC_MINALIGN struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv); /* The information at the returned address is guaranteed to be cacheline aligned */