From patchwork Tue May 3 08:58:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Cameron X-Patchwork-Id: 12835339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02B2EC433EF for ; Tue, 3 May 2022 08:58:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232140AbiECJBj (ORCPT ); Tue, 3 May 2022 05:01:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233112AbiECJBi (ORCPT ); Tue, 3 May 2022 05:01:38 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68D3036332 for ; Tue, 3 May 2022 01:58:04 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id F3F8361336 for ; Tue, 3 May 2022 08:58:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 08D60C385B1; Tue, 3 May 2022 08:57:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1651568283; bh=nPdsk11uFGgd4Jsvi2wuO7sc6TTwHPSYNSF1teGXER0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=To66ZeauVvpBWmdEy7QShWjP+5UxCCnZBV0vXGFopx/BGN8j+wtqb1ntvkg7J10Pe bkkdyz0Lec8wZUzOHuHD0iVuk4ec6XxjcLsxLTYLG66ixZUllvNYwvStfXnL9nx7Uz gm8eqwBTgdILOpRKwe2bk72H1z0HCrPF5Clj/gjaFa5w3rYsvfhSkZ+0/uvF1jlSnP 8VfOUVhMELU3OgJgDK+SGveNHaCKTzy8+RTNjYXo4Xd69N4JBNg9GsbQZiOOTveYEZ acH8LvYGj+nyozUQmuCmJYtxe05qHqeyPYh+edFxp5sWBd8SldHUUQXkhQv1c+znkR wfsMlT/1rtZsw== From: Jonathan Cameron To: linux-iio@vger.kernel.org Cc: Akinobu Mita , Alexandru Lazar , Alexandru Tachici , Antoniu Miclaus , Charles-Antoine Couret , Cosmin Tanislav , Cristian Pop , David Lechner , Ivan Mikhaylov , Jacopo Mondi , Jean-Baptiste Maneyrol , Lars-Peter Clausen , Marcelo Schmitt , =?utf-8?q?M=C3=A5rten_Lindahl?= , Matt Ranostay , Michael Hennerich , Michael Welling , Mugilraj Dhavachelvan , Navin Sankar Velliangiri , =?utf-8?q?Nuno_S=C3=A1?= , Paul Cercueil , Phil Reid , Puranjay Mohan , Ricardo Ribalda , Robert Jones , Rui Miguel Silva , Sean Nyekjaer , Tomas Melin , Tomislav Denis , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Cameron Subject: [PATCH 40/92] iio: addac: ad74413r: Fix alignment for DMA safety Date: Tue, 3 May 2022 09:58:43 +0100 Message-Id: <20220503085935.1533814-41-jic23@kernel.org> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220503085935.1533814-1-jic23@kernel.org> References: <20220503085935.1533814-1-jic23@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org From: Jonathan Cameron ____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_ALIGN definition. Update the comment to include 'may'. Fixes: fea251b6a5db ("iio: addac: add AD74413R driver") Signed-off-by: Jonathan Cameron Cc: Cosmin Tanislav --- drivers/iio/addac/ad74413r.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/addac/ad74413r.c b/drivers/iio/addac/ad74413r.c index acd230a6af35..99ddf3f4c544 100644 --- a/drivers/iio/addac/ad74413r.c +++ b/drivers/iio/addac/ad74413r.c @@ -77,13 +77,13 @@ struct ad74413r_state { struct spi_transfer adc_samples_xfer[AD74413R_CHANNEL_MAX + 1]; /* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ struct { u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; s64 timestamp; - } adc_samples_buf ____cacheline_aligned; + } adc_samples_buf __aligned(IIO_ALIGN); u8 adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX]; u8 reg_tx_buf[AD74413R_FRAME_SIZE];