| Message ID | 20220503085935.1533814-76-jic23@kernel.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | IIO: Fix alignment of buffers for DMA | expand |
Hi Jonathan, Thanks for fixing this. On Tue, May 03, 2022 at 09:59:18AM +0100, Jonathan Cameron wrote: > From: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > ____cacheline_aligned is an insufficient guarantee for non-coherent DMA > on platforms with 128 byte cachelines above L1. Switch to the updated > IIO_ALIGN definition. > > Updated the comment to 'may' require. > > Fixes: a0701b6263ae ("iio: gyro: add core driver for fxas21002c") > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Cc: Rui Miguel Silva <rui.silva@linaro.org> Reviewed-by: Rui Miguel Silva <rui.silva@linaro.org> Cheers, Rui > --- > drivers/iio/gyro/fxas21002c_core.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/iio/gyro/fxas21002c_core.c b/drivers/iio/gyro/fxas21002c_core.c > index 410e5e9f2672..d89dab48956a 100644 > --- a/drivers/iio/gyro/fxas21002c_core.c > +++ b/drivers/iio/gyro/fxas21002c_core.c > @@ -150,10 +150,10 @@ struct fxas21002c_data { > struct regulator *vddio; > > /* > - * DMA (thus cache coherency maintenance) requires the > - * transfer buffers to live in their own cache lines. > + * DMA (thus cache coherency maintenance) may require the > + * transfer buffers live in their own cache lines. > */ > - s16 buffer[8] ____cacheline_aligned; > + s16 buffer[8] __aligned(IIO_ALIGN); > }; > > enum fxas21002c_channel_index { > -- > 2.36.0 >
diff --git a/drivers/iio/gyro/fxas21002c_core.c b/drivers/iio/gyro/fxas21002c_core.c index 410e5e9f2672..d89dab48956a 100644 --- a/drivers/iio/gyro/fxas21002c_core.c +++ b/drivers/iio/gyro/fxas21002c_core.c @@ -150,10 +150,10 @@ struct fxas21002c_data { struct regulator *vddio; /* - * DMA (thus cache coherency maintenance) requires the - * transfer buffers to live in their own cache lines. + * DMA (thus cache coherency maintenance) may require the + * transfer buffers live in their own cache lines. */ - s16 buffer[8] ____cacheline_aligned; + s16 buffer[8] __aligned(IIO_ALIGN); }; enum fxas21002c_channel_index {